This code is used for creating a system design simulation stage of simulation data, the results of running a series of random numbers. Compiler can generate data generated modules, in other works as a call between the data input to the VHDL simulation involves a certain degree of help

Packet : 97288410random_number_generator.rar filelist
Random Number generator library\readme.txt
Random Number generator library\bench\vhdl\math_lib.vhd
Random Number generator library\bench\vhdl\tb_rng.vhd
Random Number generator library\bench\vhdl\rng_lib.vhd
Random Number generator library\doc\src\random_ug.doc
Random Number generator library\doc\copying.txt
Random Number generator library\bench\vhdl
Random Number generator library\doc\src
Random Number generator library\bench
Random Number generator library\doc
Random Number generator library

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