Introduction - If you have any usage issues, please Google them yourself
Verilog I2C Bus realize, including the main module and several sub-modules have been simulation
Packet : 61549830source.rar filelist
Source\i2c.v
Source\i2c_clk.v
Source\i2c_rreg.v
Source\i2c_st.v
Source\i2c_tbuf.v
Source\i2c_wreg.v
Source\transcript
Source