Packet : 39709571200711269293816.rar filelist
chap8\add8_tp.v
chap8\carry_udp.v
chap8\carry_udpx1.v
chap8\carry_udpx2.v
chap8\count8_tp.v
chap8\delay.v
chap8\dff.v
chap8\dff_udp.v
chap8\latch.v
chap8\mult_tp.v
chap8\mux31.v
chap8\mux_tp.v
chap8\random_tp.v
chap8\rom.v
chap8\test1.v
chap8\test2.v
chap8\time_dif.v
chap8
chap9\bidir.v
chap9\bidir2.v
chap9\code_83.v
chap9\decode47.v
chap9\decoder_38.v
chap9\dff.v
chap9\dff1.v
chap9\dff2.v
chap9\encoder8_3.v
chap9\gate1.v
chap9\gate2.v
chap9\gate3.v
chap9\jk_ff.v
chap9\johnson.v
chap9\latch_1.v
chap9\latch_2.v
chap9\latch_8.v
chap9\mac.v
chap9\mac_tp.v
chap9\map_lpm_ram.v
chap9\mpc.v
chap9\mpc_tp.v
chap9\mux_case.v
chap9\mux_if.v
chap9\parity.v
chap9\ram256x8.v
chap9\reg8.v
chap9\rom.v
chap9\serial_pal.v
chap9\shifter.v
chap9\tri_1.v
chap9\tri_2.v
chap9\updown_count.v
chap9
chap10\acc.v
chap10\accn.v
chap10\add8.v
chap10\adder8.v
chap10\block1.v
chap10\block2.v
chap10\block3.v
chap10\block4.v
chap10\control.v
chap10\fsm.v
chap10\longframe1.v
chap10\longframe2.v
chap10\pipeline.v
chap10\reg8.v
chap10\resource1.v
chap10\resource2.v
chap10\acc.acf
chap10\acc.hif
chap10
chap11\account.v
chap11\clock.v
chap11\count10.v
chap11\fre_ctrl.v
chap11\latch_16.v
chap11\paobiao.v
chap11\sell.v
chap11\song.v
chap11\traffic.v
chap11
chap12\add_ahead.v
chap12\add_bx.v
chap12\add_jl.v
chap12\add_tree.v
chap12\correlator.v
chap12\crc.v
chap12\cycle.v
chap12\decoder1.v
chap12\decoder2.v
chap12\fir.v
chap12\linear.v
chap12\mult.v
chap12\mult4x4.v
chap12
examples.pdf
chap3\adder4.v
chap3\adder_tp.v
chap3\aoi.v
chap3\count4.v
chap3\count4_tp.v
chap3\adder4.acf
chap3\adder4.ndb
chap3\adder4.hif
chap3
chap5\adder.v
chap5\adder16.v
chap5\alu.v
chap5\block.v
chap5\buried_ff.v
chap5\compile.v
chap5\count.v
chap5\count60.v
chap5\decode4_7.v
chap5\loop1.v
chap5\loop2.v
chap5\loop3.v
chap5\mult_for.v
chap5\mult_repeat.v
chap5\mux21_1.v
chap5\mux21_2.v
chap5\mux4_1.v
chap5\mux_casez.v
chap5\non_block.v
chap5\test.v
chap5\voter7.v
chap5\wave1.v
chap5\wave2.v
chap5\transcript
chap5\work\_info
chap5\work\decode4_7\_primary.vhd
chap5\work\decode4_7\verilog.asm
chap5\work\decode4_7\_primary.dat
chap5\work\decode4_7
chap5\work
chap5\modelsim.ini
chap5\vish_stacktrace.vstf
chap5
chap6\alutask.v
chap6\alu_tp.v
chap6\code_83.v
chap6\count.v
chap6\funct.v
chap6\funct_tp.v
chap6\paral1.v
chap6\paral2.v
chap6\serial1.v
chap6\serial2.v
chap6
chap7\add4_1.v
chap7\add4_2.v
chap7\add4_3.v
chap7\count4.v
chap7\full_add1.v
chap7\full_add2.v
chap7\full_add3.v
chap7\full_add4.v
chap7\full_add5.v
chap7\half_add1.v
chap7\half_add2.v
chap7\half_add3.v
chap7\half_add4.v
chap7\mux2_1a.v
chap7\mux2_1b.v
chap7\mux2_1c.v
chap7\mux4_1a.v
chap7\mux4_1b.v
chap7\mux4_1c.v
chap7\mux4_1d.v
chap7

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