Obstructive and non-blocking assignment on the information, very good information, in fact, differences between VHDL and Verilog do not fight

Packet : 5956444blocking_nonblocking.rar filelist
阻塞与非阻塞赋值
阻塞与非阻塞赋值\Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!.pdf
阻塞与非阻塞赋值\Verilog非阻塞赋值的仿真综合问题.pdf

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