Packet : 71477217cc.rar filelist
CC\cmp_state.ini
CC\component_builder_logfile.txt
CC\PWM.qpf
CC\PWM.qsf
CC\PWM.qws
CC\sopc_builder_debug_log.txt
CC\Test_PWM.ptf
CC\Test_PWM.ptf.bak
CC\Test_PWM.v
CC\Test_PWM.vhd
CC\pwm_test\hello_altera_avalon_pwm.c
CC\pwm_test
CC\pwm_source\pwm_sw\test_software\hello_altera_avalon_pwm.c
CC\pwm_source\pwm_sw\test_software
CC\pwm_source\pwm_sw\inc\altera_avalon_pwm_regs.h
CC\pwm_source\pwm_sw\inc
CC\pwm_source\pwm_sw\HAL\src\altera_avalon_pwm_routines.c
CC\pwm_source\pwm_sw\HAL\src
CC\pwm_source\pwm_sw\HAL\inc\altera_avalon_pwm_routines.h
CC\pwm_source\pwm_sw\HAL\inc
CC\pwm_source\pwm_sw\HAL
CC\pwm_source\pwm_sw
CC\pwm_source\pwm_hw\pwm_avalon_interface.v
CC\pwm_source\pwm_hw\pwm_register_file.v
CC\pwm_source\pwm_hw\pwm_task_logic.v
CC\pwm_source\pwm_hw
CC\pwm_source
CC\pwm_avalon_interface\cb_generator.pl
CC\pwm_avalon_interface\class.ptf
CC\pwm_avalon_interface\inc\altera_avalon_pwm_regs.h
CC\pwm_avalon_interface\inc
CC\pwm_avalon_interface\hdl\pwm_avalon_interface.v
CC\pwm_avalon_interface\hdl\pwm_register_file.v
CC\pwm_avalon_interface\hdl\pwm_task_logic.v
CC\pwm_avalon_interface\hdl
CC\pwm_avalon_interface\HAL\src\altera_avalon_pwm_routines.c
CC\pwm_avalon_interface\HAL\src\component.mk
CC\pwm_avalon_interface\HAL\src
CC\pwm_avalon_interface\HAL\inc\altera_avalon_pwm_routines.h
CC\pwm_avalon_interface\HAL\inc
CC\pwm_avalon_interface\HAL
CC\pwm_avalon_interface
CC\DeviceSOPC_StandardCore_pwm\cmp_state.ini
CC\DeviceSOPC_StandardCore_pwm\component_builder_logfile.txt
CC\DeviceSOPC_StandardCore_pwm\cpu_0.ocp
CC\DeviceSOPC_StandardCore_pwm\cpu_0.v
CC\DeviceSOPC_StandardCore_pwm\cpu_0_jtag_debug_module.v
CC\DeviceSOPC_StandardCore_pwm\cpu_0_jtag_debug_module_wrapper.v
CC\DeviceSOPC_StandardCore_pwm\cpu_0_ociram_default_contents.mif
CC\DeviceSOPC_StandardCore_pwm\cpu_0_test_bench.v
CC\DeviceSOPC_StandardCore_pwm\delay_reset_block.bdf
CC\DeviceSOPC_StandardCore_pwm\delay_reset_block.bsf
CC\DeviceSOPC_StandardCore_pwm\dma.v
CC\DeviceSOPC_StandardCore_pwm\epcs_controller.v
CC\DeviceSOPC_StandardCore_pwm\epcs_controller_boot_rom.hex
CC\DeviceSOPC_StandardCore_pwm\high_res_timer.v
CC\DeviceSOPC_StandardCore_pwm\i2c_master.v
CC\DeviceSOPC_StandardCore_pwm\i2c_master_bit_ctrl.vhd
CC\DeviceSOPC_StandardCore_pwm\i2c_master_byte_ctrl.vhd
CC\DeviceSOPC_StandardCore_pwm\i2c_master_top.vhd
CC\DeviceSOPC_StandardCore_pwm\ic_tag_ram.mif
CC\DeviceSOPC_StandardCore_pwm\jtag_uart.v
CC\DeviceSOPC_StandardCore_pwm\key_pio.v
CC\DeviceSOPC_StandardCore_pwm\led.v
CC\DeviceSOPC_StandardCore_pwm\led_pio.v
CC\DeviceSOPC_StandardCore_pwm\oc_i2c_master.vhd
CC\DeviceSOPC_StandardCore_pwm\onchip_ram.hex
CC\DeviceSOPC_StandardCore_pwm\onchip_ram.v
CC\DeviceSOPC_StandardCore_pwm\opencores_i2c_master.v
CC\DeviceSOPC_StandardCore_pwm\p0_2_p0_3.v
CC\DeviceSOPC_StandardCore_pwm\p0_7_p0_30.v
CC\DeviceSOPC_StandardCore_pwm\p1_16_p1_25.v
CC\DeviceSOPC_StandardCore_pwm\p2_16_p2_31.v
CC\DeviceSOPC_StandardCore_pwm\PLL.bsf
CC\DeviceSOPC_StandardCore_pwm\PLL.v
CC\DeviceSOPC_StandardCore_pwm\pwm.v
CC\DeviceSOPC_StandardCore_pwm\pwm_avalon_interface.v
CC\DeviceSOPC_StandardCore_pwm\pwm_register_file.v
CC\DeviceSOPC_StandardCore_pwm\pwm_task_logic.v
CC\DeviceSOPC_StandardCore_pwm\reset_counter.bsf
CC\DeviceSOPC_StandardCore_pwm\reset_counter.v
CC\DeviceSOPC_StandardCore_pwm\rf_ram_a.mif
CC\DeviceSOPC_StandardCore_pwm\rf_ram_b.mif
CC\DeviceSOPC_StandardCore_pwm\SCL.v
CC\DeviceSOPC_StandardCore_pwm\SDA.v
CC\DeviceSOPC_StandardCore_pwm\sdram.v
CC\DeviceSOPC_StandardCore_pwm\sdram_test_component.v
CC\DeviceSOPC_StandardCore_pwm\serv_req_info.txt
CC\DeviceSOPC_StandardCore_pwm\sopc_builder_debug_log.txt
CC\DeviceSOPC_StandardCore_pwm\spi.v
CC\DeviceSOPC_StandardCore_pwm\standard.asm.rpt
CC\DeviceSOPC_StandardCore_pwm\standard.bdf
CC\DeviceSOPC_StandardCore_pwm\standard.cdf
CC\DeviceSOPC_StandardCore_pwm\standard.done
CC\DeviceSOPC_StandardCore_pwm\standard.fit.eqn
CC\DeviceSOPC_StandardCore_pwm\standard.fit.rpt
CC\DeviceSOPC_StandardCore_pwm\standard.fit.summary
CC\DeviceSOPC_StandardCore_pwm\standard.fld
CC\DeviceSOPC_StandardCore_pwm\standard.flow.rpt
CC\DeviceSOPC_StandardCore_pwm\standard.jic
CC\DeviceSOPC_StandardCore_pwm\standard.map.eqn
CC\DeviceSOPC_StandardCore_pwm\standard.map.rpt
CC\DeviceSOPC_StandardCore_pwm\standard.map.summary
CC\DeviceSOPC_StandardCore_pwm\standard.pin
CC\DeviceSOPC_StandardCore_pwm\standard.pof
CC\DeviceSOPC_StandardCore_pwm\standard.ppl
CC\DeviceSOPC_StandardCore_pwm\standard.qpf
CC\DeviceSOPC_StandardCore_pwm\standard.qsf
CC\DeviceSOPC_StandardCore_pwm\standard.qsf.bak
CC\DeviceSOPC_StandardCore_pwm\standard.qws
CC\DeviceSOPC_StandardCore_pwm\standard.rbf
CC\DeviceSOPC_StandardCore_pwm\standard.sof
CC\DeviceSOPC_StandardCore_pwm\standard.tan.rpt
CC\DeviceSOPC_StandardCore_pwm\standard.tan.summary
CC\DeviceSOPC_StandardCore_pwm\standard_1c6.bsf
CC\DeviceSOPC_StandardCore_pwm\standard_1c6.ptf
CC\DeviceSOPC_StandardCore_pwm\standard_1c6.ptf.bak
CC\DeviceSOPC_StandardCore_pwm\standard_1c6.v
CC\DeviceSOPC_StandardCore_pwm\standard_1c6_generation_script
CC\DeviceSOPC_StandardCore_pwm\standard_1c6_log.txt
CC\DeviceSOPC_StandardCore_pwm\standard_1c6_setup_quartus.tcl
CC\DeviceSOPC_StandardCore_pwm\sysid.v
CC\DeviceSOPC_StandardCore_pwm\sys_clock_timer.v
CC\DeviceSOPC_StandardCore_pwm\uart.v
CC\DeviceSOPC_StandardCore_pwm\uart1.v
CC\DeviceSOPC_StandardCore_pwm\watchdog.v
CC\DeviceSOPC_StandardCore_pwm
CC\db\PWM.db_info
CC\db\PWM.eco.cdb
CC\db\PWM.sld_design_entry.sci
CC\db
CC

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