Introduction - If you have any usage issues, please Google them yourself
Using FPGA to achieve with digital watches stopwatch calendar, verilog code.
Packet : 3970984watch.rar filelist
watch\CLKGEN.V
watch\COUNTER.V
watch\dataSel.v
watch\DECODER.V
watch\MUNIT.V
watch\TIMECTL.V
watch\TOP.V
watch