This example uses a DCM module, the input clock 50MHz, frequency-doubled to 100MHz, frequency to 25MHz, the frequency of different values demonstrated through the LED.

Packet : 31767675dmc_verilog.rar filelist
xapp462_verilog\BUFG_CLK0_FB_SUBM.v
xapp462_verilog\BUFG_CLK0_SUBM.v
xapp462_verilog\BUFG_CLK2X_FB_SUBM.v
xapp462_verilog\BUFG_CLK2X_SUBM.v
xapp462_verilog\BUFG_CLKDV_SUBM.v
xapp462_verilog\BUFG_DFS_FB_SUBM.v
xapp462_verilog\BUFG_DFS_SUBM.v
xapp462_verilog\BUFG_PHASE_CLK0_SUBM.v
xapp462_verilog\BUFG_PHASE_CLK2X_SUBM.v
xapp462_verilog\BUFG_PHASE_CLKDV_SUBM.v
xapp462_verilog\BUFG_PHASE_CLKFX_FB_SUBM.v
xapp462_verilog\DCM_INST.v
xapp462_verilog\readme_dcm_verilog.txt
xapp462_verilog
xapp462.pdf

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