Described in VHDL language using single-precision floating-point processor. Web site source code from abroad. Can be achieved single precision floating point addition and subtraction, multiplication.

Packet : 13898398fpu.rar filelist
fpu\pre_norm_fmul_arch.vhd
fpu\div_r2_arch.vhd
fpu\except_arch.vhd
fpu\fpu_arch.vhd
fpu\mul_r2_arch.vhd
fpu\post_norm_arch.vhd
fpu\pre_norm_arch.vhd
fpu\add_sub27_arch.vhd
fpu\fpu_compile_scr.txt
fpu

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