An FPGA using Verilog realization of the UART interface module, including test modules and entities, and to realize the output interface and status interface.

Packet : 49636977uart.rar filelist
uart\.svn\entries
uart\.svn\format
uart\src\.svn\entries
uart\src\.svn\format
uart\src\.svn\text-base\glbl.v.svn-base
uart\src\.svn\text-base\receive.v.svn-base
uart\src\.svn\text-base\transmit.v.svn-base
uart\src\.svn\text-base\uart.v.svn-base
uart\src\glbl.v
uart\src\receive.v
uart\src\transmit.v
uart\src\uart.v
uart\test\.svn\entries
uart\test\.svn\format
uart\test\.svn\text-base\receive_tb.v.svn-base
uart\test\.svn\text-base\transmit_tb.v.svn-base
uart\test\.svn\text-base\uart_tb.v.svn-base
uart\test\receive_tb.v
uart\test\transmit_tb.v
uart\test\uart_tb.v
uart\test_with_pc\.svn\entries
uart\test_with_pc\.svn\format
uart\test_with_pc\.svn\text-base\test.v.svn-base
uart\test_with_pc\.svn\text-base\uart_test_9600.v.svn-base
uart\test_with_pc\test.v
uart\test_with_pc\uart_test_9600.v
uart\src\.svn\tmp\prop-base
uart\src\.svn\tmp\props
uart\src\.svn\tmp\text-base
uart\test\.svn\tmp\prop-base
uart\test\.svn\tmp\props
uart\test\.svn\tmp\text-base
uart\test_with_pc\.svn\tmp\prop-base
uart\test_with_pc\.svn\tmp\props
uart\test_with_pc\.svn\tmp\text-base
uart\.svn\tmp\prop-base
uart\.svn\tmp\props
uart\.svn\tmp\text-base
uart\src\.svn\prop-base
uart\src\.svn\props
uart\src\.svn\text-base
uart\src\.svn\tmp
uart\test\.svn\prop-base
uart\test\.svn\props
uart\test\.svn\text-base
uart\test\.svn\tmp
uart\test_with_pc\.svn\prop-base
uart\test_with_pc\.svn\props
uart\test_with_pc\.svn\text-base
uart\test_with_pc\.svn\tmp
uart\.svn\prop-base
uart\.svn\props
uart\.svn\text-base
uart\.svn\tmp
uart\src\.svn
uart\test\.svn
uart\test_with_pc\.svn
uart\.svn
uart\src
uart\test
uart\test_with_pc
uart

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