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  • Update : 2008-10-13
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Can prefetch the fifo of the FPGA design code, to meet the asynchronous clock operation
Packet file list
(Preview for download)
Packet : 79419113vr_fifo.rar filelist
doc\VR_FIFO_spec.doc
doc
par\.recordref
par\layer0.sro
par\layer0.tlg
par\rpt_vr_fifo.areasrr
par\rpt_vr_fifo_areasrr.htm
par\stderr.log
par\stdout.log
par\syntmp\vr_fifo.msg
par\syntmp\vr_fifo.plg
par\syntmp\vr_fifo_flink.htm
par\syntmp\vr_fifo_srr.htm
par\syntmp\vr_fifo_toc.htm
par\syntmp
par\traplog.tlg
par\verif\vr_fifo.vif
par\verif
par\vr_fifo.bld
par\vr_fifo.cel
par\vr_fifo.cmd_log
par\vr_fifo.edn
par\vr_fifo.fse
par\vr_fifo.htm
par\vr_fifo.ise
par\vr_fifo.ise_created
par\vr_fifo.ise_ISE_Backup
par\vr_fifo.log
par\vr_fifo.ncd
par\vr_fifo.ncf
par\vr_fifo.ngd
par\vr_fifo.pad
par\vr_fifo.par
par\vr_fifo.pcf
par\vr_fifo.prj
par\vr_fifo.sdc
par\vr_fifo.srd
par\vr_fifo.srm
par\vr_fifo.srr
par\vr_fifo.srs
par\vr_fifo.twr
par\vr_fifo.twx
par\vr_fifo.ucf
par\vr_fifo.unroutes
par\vr_fifo.xpi
par\vr_fifo_compile.tcl
par\vr_fifo_last_par.ncd
par\vr_fifo_map.mrp
par\vr_fifo_map.ncd
par\vr_fifo_map.ngm
par\vr_fifo_map.tcl
par\vr_fifo_pad.csv
par\vr_fifo_pad.txt
par\vr_fifo_summary.html
par\_mh_info
par\_ngo\netlist.lst
par\_ngo\vr_fifo.ngo
par\_ngo
par\_verilog_hintfile
par\_xmsgs\map.xmsgs
par\_xmsgs\ngdbuild.xmsgs
par\_xmsgs\par.xmsgs
par\_xmsgs\trce.xmsgs
par\_xmsgs\xst.xmsgs
par\_xmsgs
par\__ISE_repository_vr_fifo.ise_.lock
par
sim\sim.do
sim\vsim.wlf
sim\wave.do
sim\work\polynome_pkg\body.asm
sim\work\polynome_pkg\body.dat
sim\work\polynome_pkg\_primary.dat
sim\work\polynome_pkg\_vhdl.asm
sim\work\polynome_pkg
sim\work\vr_fifo\rtl.asm
sim\work\vr_fifo\rtl.dat
sim\work\vr_fifo\_primary.dat
sim\work\vr_fifo
sim\work\vr_fifo_tb\bench.asm
sim\work\vr_fifo_tb\bench.dat
sim\work\vr_fifo_tb\_primary.dat
sim\work\vr_fifo_tb
sim\work\_info
sim\work
sim
src\vr_fifo_rtl.vhd
src
bench\polynome_pkg.vhd
bench\polynome_pkg_body.vhd
bench\vr_fifo_tb.vhd
bench
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