Introduction - If you have any usage issues, please Google them yourself
AD976 ADC sampling procedures Verilog realize the controller, based on the state machine to achieve
Packet : 27796706adccaiyang.rar filelist
ADCcaiyang\.sopc_builder\install.ptf
ADCcaiyang\ADC.asm.rpt
ADCcaiyang\ADC.done
ADCcaiyang\ADC.fit.rpt
ADCcaiyang\ADC.fit.smsg
ADCcaiyang\ADC.fit.summary
ADCcaiyang\ADC.flow.rpt
ADCcaiyang\ADC.map.rpt
ADCcaiyang\ADC.map.summary
ADCcaiyang\ADC.pin
ADCcaiyang\ADC.pof
ADCcaiyang\ADC.qpf
ADCcaiyang\ADC.qsf
ADCcaiyang\ADC.qws
ADCcaiyang\ADC.sim.rpt
ADCcaiyang\ADC.sof
ADCcaiyang\ADC.tan.rpt
ADCcaiyang\ADC.tan.summary
ADCcaiyang\ADC.v
ADCcaiyang\ADC.vwf
ADCcaiyang\db\ADC.(0).cnf.cdb
ADCcaiyang\db\ADC.(0).cnf.hdb
ADCcaiyang\db\ADC.asm.qmsg
ADCcaiyang\db\ADC.cbx.xml
ADCcaiyang\db\ADC.cmp.cdb
ADCcaiyang\db\ADC.cmp.hdb
ADCcaiyang\db\ADC.cmp.kpt
ADCcaiyang\db\ADC.cmp.rdb
ADCcaiyang\db\ADC.cmp.tdb
ADCcaiyang\db\ADC.cmp0.ddb
ADCcaiyang\db\ADC.dbp
ADCcaiyang\db\ADC.db_info
ADCcaiyang\db\ADC.eco.cdb
ADCcaiyang\db\ADC.eds_overflow
ADCcaiyang\db\ADC.fit.qmsg
ADCcaiyang\db\ADC.hier_info
ADCcaiyang\db\ADC.hif
ADCcaiyang\db\ADC.map.cdb
ADCcaiyang\db\ADC.map.hdb
ADCcaiyang\db\ADC.map.qmsg
ADCcaiyang\db\ADC.pre_map.cdb
ADCcaiyang\db\ADC.pre_map.hdb
ADCcaiyang\db\ADC.psp
ADCcaiyang\db\ADC.pss
ADCcaiyang\db\ADC.rtlv.hdb
ADCcaiyang\db\ADC.rtlv_sg.cdb
ADCcaiyang\db\ADC.rtlv_sg_swap.cdb
ADCcaiyang\db\ADC.sgdiff.cdb
ADCcaiyang\db\ADC.sgdiff.hdb
ADCcaiyang\db\ADC.signalprobe.cdb
ADCcaiyang\db\ADC.sim.hdb
ADCcaiyang\db\ADC.sim.qmsg
ADCcaiyang\db\ADC.sim.rdb
ADCcaiyang\db\ADC.sim.vwf
ADCcaiyang\db\ADC.sld_design_entry.sci
ADCcaiyang\db\ADC.sld_design_entry_dsc.sci
ADCcaiyang\db\ADC.syn_hier_info
ADCcaiyang\db\ADC.tan.qmsg
ADCcaiyang\db\wed.zsf
ADCcaiyang\sopc_builder_debug_log.txt
ADCcaiyang\.sopc_builder
ADCcaiyang\db
ADCcaiyang