This source code is a check node unit for LDPC decoder. The language is Verilog HDL.

bench\verilog\tb_bit_serial.v
.....\.......\tb_bit_serial.v.bak
.....\.......\tb_bit_serial_withXOR.v
.....\.......\tb_bit_serial_withXOR.v.bak
.....\.......\tb_FAID_sub_MF.v
.....\.......\tb_FAID_sub_MF.v.bak
.....\.......\tb_mVG_8.v
.....\.......\tb_mVG_8.v.bak
.....\.......\tb_new2_cont.v
.....\.......\tb_new2_cont.v.bak
.....\.......\tb_new2_top_test_pro_min.v
.....\.......\tb_new2_top_test_pro_min.v.bak
.....\.......\tb_new_top_test_pro_min.v
.....\.......\tb_temp.v
.....\.......\tb_temp.v.bak
.....\.......\tb_temp2.v
.....\.......\tb_temp2.v.bak
design\verilog\Bit-serial.v
......\.......\bit_serial.v
......\.......\bit_serial.v.bak
......\.......\bit_serial_finder.v
......\.......\bit_serial_finder.v.bak
......\.......\bit_serial_withXOR.v
......\.......\bit_serial_withXOR.v.bak
......\.......\CU.v
......\.......\CU.v.bak
......\.......\FAID_sub_MF.v
......\.......\FAID_sub_MF.v.bak
......\.......\mVG_16.v
......\.......\mVG_16.v.bak
......\.......\mVG_2.v
......\.......\mVG_2.v.bak
......\.......\mVG_32.v
......\.......\mVG_32.v.bak
......\.......\mVG_4.v
......\.......\mVG_4.v.bak
......\.......\mVG_64.v
......\.......\mVG_64.v.bak
......\.......\mVG_8.v
......\.......\mVG_8.v.bak
......\.......\mVU.v
......\.......\mVU.v.bak
......\.......\new2_cont.v
......\.......\new2_cont.v.bak
......\.......\new2_top_test_pro_min.v
......\.......\new2_top_test_pro_min.v.bak
......\.......\new_flag_module.v
......\.......\new_flag_module.v.bak
......\.......\new_sel_gen.v
......\.......\new_sel_gen.v.bak
......\.......\new_top_flag.v
......\.......\new_top_flag.v.bak
......\.......\new_top_test_pro_min.v
......\.......\new_top_test_pro_min.v.bak
......\.......\priencr.v
......\.......\priencr.v.bak
......\.......\recursive_test.v
......\.......\temp.v
......\.......\temp.v.bak
......\.......\temp2.v
......\.......\temp2.v.bak
......\.......\UZD.v
......\.......\UZD.v.bak
......\.......\XOR_tree.v
......\.......\XOR_tree.v.bak
ise\AutoConstraint_bit_serial.sdc
...\AutoConstraint_bit_serial_finder.sdc
...\AutoConstraint_bit_serial_withXOR.sdc
...\AutoConstraint_FAID_sub_MF.sdc
...\AutoConstraint_mVG_16.sdc
...\AutoConstraint_mVG_32.sdc
...\AutoConstraint_mVG_4.sdc
...\AutoConstraint_mVG_64.sdc
...\AutoConstraint_new2_cont.sdc
...\AutoConstraint_new2_top_test_pro_min.sdc
...\AutoConstraint_new_top_test_pro_min.sdc
...\AutoConstraint_temp.sdc
...\AutoConstraint_temp2.sdc
...\AutoConstraint_UZD.sdc
...\AutoConstraint_XOR_tree.sdc
...\backup\bit_serial.srr
...\......\bit_serial_finder.srr
...\......\bit_serial_withXOR.srr
...\......\FAID_sub_MF.srr
...\......\mVG_2k.srr
...\......\mVG_4.srr
...\......\mVG_64.srr
...\......\new2_cont.srr
...\......\new2_top_test_pro_min.srr
...\......\new_top_test_pro_min.srr
...\......\temp.srr
...\......\temp2.srr
...\......\UZD.srr
...\......\XOR_tree.srr
...\bit_serial.fse
...\bit_serial.htm
...\bit_serial.map
...\bit_serial.sap
...\bit_serial.sdc
...\bit_serial.szr

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