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I have just completed development environment based on the Quartus Two full use Verilog hardware descr iption language compiler unmistakable MSK modem
Packet : 476514762400verilog.rar filelist
2400verilog\2400verilog.qpf
2400verilog\2400verilog.qsf
2400verilog\mzk.qar
2400verilog\2400verilog.v
2400verilog\2400verilog.map.rpt
2400verilog\2400verilog.flow.rpt
2400verilog\2400verilog.map.summary
2400verilog\mzk.v
2400verilog\mzk.qarlog
2400verilog\mzk.qpf
2400verilog\2400verilog.qws
2400verilog\mzk.qws
2400verilog\db\2400verilog.db_info
2400verilog\db\2400verilog.map.qmsg
2400verilog\db\2400verilog.eco.cdb
2400verilog\db\2400verilog.qpf
2400verilog\db\2400verilog.cbx.xml
2400verilog\db\2400verilog.map.hdb
2400verilog\db\2400verilog.cmp.rdb
2400verilog\db\2400verilog.sld_design_entry.sci
2400verilog\db
2400verilog