AC97 chip Verilog realize, who are interested can study. Verilog is a hardware development language, grammar and c similar. IC with VHDL as a programming language to develop two

Packet : 49636947ac97_verilog_sourcecode.rar filelist
ac97_ctrl\bench\CVS\Entries
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ac97_ctrl\bench\CVS\Repository
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ac97_ctrl\bench\CVS\Template
ac97_ctrl\bench\CVS
ac97_ctrl\bench\verilog\ac97_codec_sin.v
ac97_ctrl\bench\verilog\ac97_codec_sout.v
ac97_ctrl\bench\verilog\ac97_codec_top.v
ac97_ctrl\bench\verilog\CVS\Entries
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ac97_ctrl\bench\verilog\CVS
ac97_ctrl\bench\verilog\tests.v
ac97_ctrl\bench\verilog\test_bench_top.v
ac97_ctrl\bench\verilog\wb_mast_model.v
ac97_ctrl\bench\verilog\wb_model_defines.v
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ac97_ctrl\rtl\verilog\ac97_dma_if.v
ac97_ctrl\rtl\verilog\ac97_dma_req.v
ac97_ctrl\rtl\verilog\ac97_fifo_ctrl.v
ac97_ctrl\rtl\verilog\ac97_int.v
ac97_ctrl\rtl\verilog\ac97_in_fifo.v
ac97_ctrl\rtl\verilog\ac97_out_fifo.v
ac97_ctrl\rtl\verilog\ac97_prc.v
ac97_ctrl\rtl\verilog\ac97_rf.v
ac97_ctrl\rtl\verilog\ac97_rst.v
ac97_ctrl\rtl\verilog\ac97_sin.v
ac97_ctrl\rtl\verilog\ac97_soc.v
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ac97_ctrl\rtl\verilog\ac97_top.v
ac97_ctrl\rtl\verilog\ac97_wb_if.v
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ac97_ctrl

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