The new 32 booth multiplier implementations

Booth_mutipler\src\tbooth_com.v
..............\...\booth_com.v
..............\...\tbooth_pipeline.v
..............\...\booth_pipeline.v
..............\src
..............\.im\work\_info
..............\...\....\booth_pipeline\_primary.vhd
..............\...\....\..............\verilog.asm
..............\...\....\..............\_primary.dat
..............\...\....\booth_pipeline
..............\...\....\tbooth_pipeline\_primary.vhd
..............\...\....\...............\verilog.asm
..............\...\....\...............\_primary.dat
..............\...\....\tbooth_pipeline
..............\...\....\.......com\_primary.vhd
..............\...\....\..........\verilog.asm
..............\...\....\..........\_primary.dat
..............\...\....\tbooth_com
..............\...\....\booth_com\_primary.vhd
..............\...\....\.........\verilog.asm
..............\...\....\.........\_primary.dat
..............\...\....\booth_com
..............\...\work
..............\...\vsim.wlf
..............\...\booth_mul.cr.mti
..............\...\vlog.opt
..............\...\maxii\_info
..............\...\.....\@m@a@x@i@i_@p@r@i@m_@d@f@f@e\_primary.vhd
..............\...\.....\............................\verilog.asm
..............\...\.....\............................\_primary.dat
..............\...\.....\@m@a@x@i@i_@p@r@i@m_@d@f@f@e
..............\...\.....\maxii_dffe\_primary.vhd
..............\...\.....\..........\verilog.asm
..............\...\.....\..........\_primary.dat
..............\...\.....\maxii_dffe
..............\...\.....\......latch\_primary.vhd
..............\...\.....\...........\verilog.asm
..............\...\.....\...........\_primary.dat
..............\...\.....\maxii_latch
..............\...\.....\......mux21\_primary.vhd
..............\...\.....\...........\verilog.asm
..............\...\.....\...........\_primary.dat
..............\...\.....\maxii_mux21
..............\...\.....\.........41\_primary.vhd
..............\...\.....\...........\verilog.asm
..............\...\.....\...........\_primary.dat
..............\...\.....\maxii_mux41
..............\...\.....\......and1\_primary.vhd
..............\...\.....\..........\verilog.asm
..............\...\.....\..........\_primary.dat
..............\...\.....\maxii_and1
..............\...\.....\..........6\_primary.vhd
..............\...\.....\...........\verilog.asm
..............\...\.....\...........\_primary.dat
..............\...\.....\maxii_and16
..............\...\.....\......bmux21\_primary.vhd
..............\...\.....\............\verilog.asm
..............\...\.....\............\_primary.dat
..............\...\.....\maxii_bmux21
..............\...\.....\.......17mux21\_primary.vhd
..............\...\.....\..............\verilog.asm
..............\...\.....\..............\_primary.dat
..............\...\.....\maxii_b17mux21
..............\...\.....\......nmux21\_primary.vhd
..............\...\.....\............\verilog.asm
..............\...\.....\............\_primary.dat
..............\...\.....\maxii_nmux21
..............\...\.....\......b5mux21\_primary.vhd
..............\...\.....\.............\verilog.asm
..............\...\.....\.............\_primary.dat
..............\...\.....\maxii_b5mux21
..............\...\.....\......asynch_lcell\_primary.vhd
..............\...\.....\..................\verilog.asm
..............\...\.....\..................\_primary.dat
..............\...\.....\maxii_asynch_lcell
..............\...\.....\......lcell_register\_primary.vhd
..............\...\.....\....................\verilog.asm
..............\...\.....\....................\_primary.dat
..............\...\.....\maxii_lcell_register
..............\...\.....\...........\_primary.vhd
..............\...\.....\...........\verilog.asm
..............\...\.....\...........\_primary.dat
..............\...\.....\maxii_lcell
..............\...\.....\......ufm\_primary.vhd
..............\...\.....\.........\verilog.asm
..............\...\.....\.........\_primary.dat
..............\...\.....\maxii_ufm
..............\...\.....\......io\_primary.vhd
..............\...\.....\........\v

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