Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementation 4_2 compressor to achieve and realize China Clarence tree, and two testbench file with the to the test.

multiply\_42c_l.v
........\boot_mul.v
........\bootcoder.v
........\csa.v
........\tb_bootmul.v
........\tb_mul.v

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