Achieved using VERILOG hardware divider. Provide RTL code and simulation files.

divider_VERILOG\bench\verilog\bench_div_top.v
...............\.....\.......\timescale.v
...............\rtl\verilog\bench_div_top.v
...............\...\.......\div.v
...............\...\.......\div_su.v
...............\...\.......\div_us.v
...............\...\.......\div_uu.v
...............\...\.......\mydiv\bench_div_top_summary.html
...............\...\.......\.....\div_su.cmd_log
...............\...\.......\.....\div_su.lso
...............\...\.......\.....\div_su.prj
...............\...\.......\.....\div_su.syr
...............\...\.......\.....\div_su.xst
...............\...\.......\.....\div_su_envsettings.html
...............\...\.......\.....\div_su_summary.html
...............\...\.......\.....\div_su_xst.xrpt
...............\...\.......\.....\iseconfig\div_su.xreport
...............\...\.......\.....\.........\mydiv.projectmgr
...............\...\.......\.....\mydiv.gise
...............\...\.......\.....\mydiv.xise
...............\...\.......\.....\webtalk_pn.xml
...............\...\.......\.....\_xmsgs\pn_parser.xmsgs
...............\...\.......\.....\......\xst.xmsgs
...............\...\.......\timescale.v
...............\...\.......\work\bench_div_top\_primary.dat
...............\...\.......\....\.............\_primary.dbs
...............\...\.......\....\.............\_primary.vhd
...............\...\.......\....\div\_primary.dat
...............\...\.......\....\...\_primary.dbs
...............\...\.......\....\...\_primary.vhd
...............\...\.......\....\..._su\_primary.dat
...............\...\.......\....\......\_primary.dbs
...............\...\.......\....\......\_primary.vhd
...............\...\.......\....\....uu\_primary.dat
...............\...\.......\....\......\_primary.dbs
...............\...\.......\....\......\_primary.vhd
...............\...\.......\....\_info
...............\...\.......\....\.temp\vlog36q5ce
...............\...\.......\....\.....\vlog5cmmwx
...............\...\.......\....\.....\vlog5dndw5
...............\...\.......\....\.....\vlog9ir2xh
...............\...\.......\....\.....\vlogbx6c65
...............\...\.......\....\.....\vlogbxxc68
...............\...\.......\....\.....\vlogf3vc11
...............\...\.......\....\.....\vlogfeyhyj
...............\...\.......\....\.....\vloggx7si4
...............\...\.......\....\.....\vloggy32jb
...............\...\.......\....\.....\vlogjad66e
...............\...\.......\....\.....\vlogjqjnv3
...............\...\.......\....\.....\vlogmcb0ay
...............\...\.......\....\.....\vlogmsx0v2
...............\...\.......\....\.....\vlogmx4h21
...............\...\.......\....\.....\vlogqeq0ty
...............\...\.......\....\.....\vlogsaefkc
...............\...\.......\....\.....\vlogvy0f87
...............\...\.......\....\.....\vlogwggzw2
...............\...\.......\....\.....\vlogwx5nc8
...............\...\.......\....\.....\vlogy62410
...............\...\.......\....\.....\vlogy62ef2
...............\...\.......\....\_vmake
...............\...\.......\mydiv\xst\projnav.tmp
...............\...\.......\.....\iseconfig
...............\...\.......\.....\xst
...............\...\.......\.....\_xmsgs
...............\...\.......\work\bench_div_top
...............\...\.......\....\div
...............\...\.......\....\div_su
...............\...\.......\....\div_uu
...............\...\.......\....\_temp
...............\...\.......\mydiv
...............\...\.......\work
...............\bench\verilog
...............\rtl\verilog
...............\bench
...............\rtl
divider_VERILOG

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