Based the ProASIC3 StartKit development board, using Verilog language description of a stopwatch counter.

mb\designer\impl1\designer.log
..\........\.....\designer_genhdl.log
..\........\.....\simulation\postlayout\top\verilog.psm
..\........\.....\..........\..........\...\_primary.dat
..\........\.....\..........\..........\...\_primary.dbs
..\........\.....\..........\..........\...\_primary.vhd
..\........\.....\..........\..........\_info
..\........\.....\top.adb
..\........\.....\....dtf\verify.log
..\........\.....\top.ide_des
..\........\.....\top.pdb
..\........\.....\top.pdb.depends
..\........\.....\top.tcl
..\........\.....\top_1.adb
..\........\.....\......dtf\verify.log
..\........\.....\top_1.ide_des
..\........\.....\top_1.pdb
..\........\.....\top_1.pdb.depends
..\........\.....\top_1_ba.sdf
..\........\.....\top_1_ba.v
..\........\.....\......fp\$$FlashPro_09003.L$$
..\........\.....\........\projectData\top_1.pdb
..\........\.....\........\top_1.log
..\........\.....\........\top_1.pro
..\........\.....\top_2.adb
..\........\.....\......dtf\verify.log
..\........\.....\top_2.ide_des
..\........\.....\top_2.pdb
..\........\.....\top_2.pdb.depends
..\........\.....\top_2_ba.sdf
..\........\.....\top_2_ba.v
..\........\.....\......fp\$$FlashPro_09003.L$$
..\........\.....\........\projectData\top_2.pdb
..\........\.....\........\top_2.log
..\........\.....\........\top_2.pro
..\........\.....\top_3.adb
..\........\.....\......dtf\verify.log
..\........\.....\top_3.ide_des
..\........\.....\top_3.pdb
..\........\.....\top_3.pdb.depends
..\........\.....\top_3_ba.sdf
..\........\.....\top_3_ba.v
..\........\.....\......fp\$$FlashPro_09003.L$$
..\........\.....\........\projectData\top_3.pdb
..\........\.....\........\top_3.log
..\........\.....\........\top_3.pro
..\........\.....\top_ba.sdf
..\........\.....\top_ba.v
..\........\.....\....fp\$$FlashPro_09003.L$$
..\........\.....\......\projectData\top.pdb
..\........\.....\......\top.log
..\........\.....\......\top.pro
..\hdl\js.v
..\...\latch.v
..\...\top.v
..\mb.prj
..\simulation\modelsim.ini
..\..........\modelsim.ini.sav
..\..........\modelsim.log
..\..........\postsynth\display\verilog.psm
..\..........\.........\.......\_primary.dat
..\..........\.........\.......\_primary.dbs
..\..........\.........\.......\_primary.vhd
..\..........\.........\js\verilog.psm
..\..........\.........\..\_primary.dat
..\..........\.........\..\_primary.dbs
..\..........\.........\..\_primary.vhd
..\..........\.........\latch\verilog.psm
..\..........\.........\.....\_primary.dat
..\..........\.........\.....\_primary.dbs
..\..........\.........\.....\_primary.vhd
..\..........\.........\top\verilog.psm
..\..........\.........\...\_primary.dat
..\..........\.........\...\_primary.dbs
..\..........\.........\...\_primary.vhd
..\..........\.........\_info
..\..........\.resynth\js\verilog.psm
..\..........\........\..\_primary.dat
..\..........\........\..\_primary.dbs
..\..........\........\..\_primary.vhd
..\..........\........\latch\verilog.psm
..\..........\........\.....\_primary.dat
..\..........\........\.....\_primary.dbs
..\..........\........\.....\_primary.vhd
..\..........\........\top\verilog.psm
..\..........\........\...\_primary.dat
..\..........\........\...\_primary.dbs
..\..........\........\...\_primary.vhd
..\..........\........\_info
..\..........\run.do
..\..........\vsim.wlf
..\..........\work\display\verilog.psm
..\..........\....\.......\_primary.dat
..\..........\....\.......\_primary.dbs
..\..........\....\.......\_primary.vhd
..\..........\....\js\verilog.psm
..\..........\....\..\_primary.dat
..\..........\....\..\_primary.dbs
..\..........\....\..\_primary.vhd
..\..........\....\latch\verilog.psm

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