MIPS VHDL Microprocessor without Interlocked Pipeline Stages

mips-vhdl
.........\asm
.........\...\example.out
.........\cpu.vhd
.........\cpu.vhd.bak
.........\DataMemory.vhd
.........\DataMemory.vhd.bak
.........\InstrMemory.vhd
.........\InstrMemory.vhd.bak
.........\MIPS-SingleClock.cr.mti
.........\MIPS-SingleClock.mpf
.........\reg.vhd.bak
.........\testbench.vhd
.........\testbench.vhd.bak
.........\transcript
.........\vsim.wlf
.........\work
.........\....\@_opt
.........\....\.....\vopt0m5a9h
.........\....\.....\vopt0r2d28
.........\....\.....\vopt0y4698
.........\....\.....\vopt35v79h
.........\....\.....\vopt77c438
.........\....\.....\vopt7saf64
.........\....\.....\voptag9ymf
.........\....\.....\voptb90c64
.........\....\.....\voptbq1138
.........\....\.....\vopte7qx28
.........\....\.....\voptee7vvc
.........\....\.....\voptfsm964
.........\....\.....\vopthywrvc
.........\....\.....\voptir9374
.........\....\.....\voptirx8vj
.........\....\.....\voptm72q28
.........\....\.....\voptn8j5vj
.........\....\.....\vopts7jt74
.........\....\.....\voptskth9h
.........\....\.....\voptsqqk28
.........\....\.....\vopttr81vj
.........\....\.....\voptw4ge9h
.........\....\.....\voptwdf998
.........\....\.....\voptwq8n74
.........\....\.....\voptx7dg28
.........\....\.....\voptx9me97
.........\....\.....\voptxbis5c
.........\....\.....\_deps
.........\....\adder
.........\....\.....\adder_behavior.dat
.........\....\.....\adder_behavior.dbs
.........\....\.....\_primary.dat
.........\....\.....\_primary.dbs
.........\....\alu
.........\....\...\alu_behavior.dat
.........\....\...\alu_behavior.dbs
.........\....\...\_primary.dat
.........\....\...\_primary.dbs
.........\....\alu_control
.........\....\...........\alucontrol_behavior.dat
.........\....\...........\alucontrol_behavior.dbs
.........\....\...........\_primary.dat
.........\....\...........\_primary.dbs
.........\....\control
.........\....\.......\control_behavior.dat
.........\....\.......\control_behavior.dbs
.........\....\.......\_primary.dat
.........\....\.......\_primary.dbs
.........\....\data_mem
.........\....\........\behavior_data_mem.dat
.........\....\........\behavior_data_mem.dbs
.........\....\........\_primary.dat
.........\....\........\_primary.dbs
.........\....\incr4
.........\....\.....\incr4_behavior.dat
.........\....\.....\incr4_behavior.dbs
.........\....\.....\_primary.dat
.........\....\.....\_primary.dbs
.........\....\instr_mem
.........\....\.........\behavior_instr_mem.dat
.........\....\.........\behavior_instr_mem.dbs
.........\....\.........\_primary.dat
.........\....\.........\_primary.dbs
.........\....\mips_cpu
.........\....\........\cpu_structure.dat
.........\....\........\cpu_structure.dbs
.........\....\........\_primary.dat
.........\....\........\_primary.dbs
.........\....\mips_tb
.........\....\.......\sim.dat
.........\....\.......\sim.dbs
.........\....\.......\_primary.dat
.........\....\.......\_primary.dbs
.........\....\mux2to1
.........\....\.......\mux2to1_behavior.dat
.........\....\.......\mux2to1_behavior.dbs
.........\....\.......\_primary.dat
.........\....\.......\_primary.dbs
.........\....\reg
.........\....\...\reg_behavior.dat
.........\....\...\reg_behavior.dbs
.........\....\...\_primary.dat

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