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DSP_TURBO Downloaded：0: Log_MAP based algorithms, a DSP to achieve the program TURBO code. The use of inline functions, the cycle started, the software pipelining algorithm is optimized, in the TMS320C6416 chip has been realized in the encoding
Date : 2008-10-13 Size : 476.92kb User : ynhuyong
TR_1342 Downloaded：0: simplescaler (RISC processor simulation analysis procedures) design documents. Note: English documentation
Date : 2008-10-13 Size : 78.31kb User : 吕奔
acquire_knowledge_base_on_internet Downloaded：0: Artificial intelligence, Internet-based data collection of knowledge acquisition. Including the semantic tree analysis details. On all aspects of knowledge acquisition has a more complete description and introduction.
Date : 2008-10-13 Size : 3.51mb User : huangbo
SD_drv Downloaded：0: The development of SD Card SD Card SD Card Development Development
Date : 2008-10-13 Size : 332.65kb User : 李林
OP Downloaded：0: opa合辑use of audio and signal amplification circuit design helpful
Date : 2008-10-13 Size : 3.07mb User : pixychu
red_decode Downloaded：0: Important to introduce a common infrared remote control on the encoding, as long as the use of one if the infrared module is very easy to accept the decoder, which has in paragraph 51 of the procedures described in detai
Date : 2008-10-13 Size : 128.19kb User : 王明
CummingsSNUG2002SJ_FIFO1 Downloaded：0: The asynchronous FIFO design for the relatively good a document, a total of 2, this is the first.
Date : 2008-10-13 Size : 116.95kb User : 王辉
CummingsSNUG2002SJ_FIFO2 Downloaded：0: This is a good document for designing asynchronous FIFO, two in total, and this is the second.
Date : 2008-10-13 Size : 99.24kb User : 王辉
DDR_SDRAM Downloaded：0: For the design of the DDSRAM have great help, I hope you can help.
Date : 2008-10-13 Size : 463.37kb User : 王辉
asynchronous_FIFO_01to03_CHN Downloaded：0: This is the design of better asynchronous FIFO a reference, I hope can be useful to everyone.
Date : 2008-10-13 Size : 532.91kb User : 王辉
FPGA Downloaded：0: FPGA to do a few video projects on paper, in the hope that everyone has to help
Date : 2008-10-13 Size : 540kb User : hbsun
multi_clock_design_in_large_scale_FPGA Downloaded：0: Realize large-scale use of FPGA design, may need to FPGA with multiple clocks to run multiple data path, the multi-clock FPGA design must be particularly careful to note the maximum clock rate, jitter, the largest number
Date : 2008-10-13 Size : 99.69kb User : mayang

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