FPGA-based I2C bus simulation, using verilog HDL language.- Based on the FPGA I2C main line simulation, verilog uses the HDL language compilation.

Packet : 337531691_061026140305.rar filelist
RD1006\Document\rd1006.pdf
RD1006\Document
RD1006\Source\i2c.v
RD1006\Source\i2c_clk.v
RD1006\Source\i2c_rreg.v
RD1006\Source\i2c_st.v
RD1006\Source\i2c_tbuf.v
RD1006\Source\i2c_wreg.v
RD1006\Source\transcript
RD1006\Source
RD1006\TestFixture\clk_rst.v
RD1006\TestFixture\i2c_slave.v
RD1006\TestFixture\i2c_tb.v
RD1006\TestFixture\micro.v
RD1006\TestFixture
RD1006

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．