Introduction - If you have any usage issues, please Google them yourself
DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Packet : 5956441ddr_sdram_controller.rar filelist
rd1020_DDR SDRAM Controller\DDR SDRAM Controller.files\arrow.gif
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rd1020_DDR SDRAM Controller\DDR SDRAM Controller.files\ddr_controller.gif
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rd1020_DDR SDRAM Controller\DDR SDRAM Controller.htm
rd1020_DDR SDRAM Controller\rd1020.pdf
rd1020_DDR SDRAM Controller\source\ddr_ctrl.v
rd1020_DDR SDRAM Controller\source\ddr_data.v
rd1020_DDR SDRAM Controller\source\ddr_par.v
rd1020_DDR SDRAM Controller\source\ddr_pll_orca.v
rd1020_DDR SDRAM Controller\source\ddr_pll_orca_sp.v
rd1020_DDR SDRAM Controller\source\ddr_sig.v
rd1020_DDR SDRAM Controller\source\ddr_top.v
rd1020_DDR SDRAM Controller\testbench\ddr_tb.v
rd1020_DDR SDRAM Controller\testbench\stimulus.v
rd1020_DDR SDRAM Controller\DDR SDRAM Controller.files
rd1020_DDR SDRAM Controller\source
rd1020_DDR SDRAM Controller\testbench
rd1020_DDR SDRAM Controller