Introduction - If you have any usage issues, please Google them yourself
wARM ARM7TDMI compatible instruction set, architecture and nnARM same, After downloading directly Simulation
Packet : 115157699warm.rar filelist
test\work.mpf
test\CanGoGen.v
test\Comp.v
test\IT.v
test\IF.v
test\ID.v
test\vsim.wlf
test\BarrelShift.v
test\Arbiter_WB.v
test\IP.v
test\Adder.v
test\w_tb.v
test\Mul.v
test\wrx.do
test\Mem_ctrl.v
test\ASC
test\PSR.v
test\wARMCore.v
test\wARM1.v
test\MEM.v
test\Def.v
test\RF.v
test\I_Bus2Core.v
test\ALUss.v
test\PSR_new.v
test\ALUcc.v
test\T2w.v
test\D_Bus2Core.v
test\transcript
test\wARM体系结构.pdf
test\wARM仿真分析.pdf
test\work.cr.mti
test\tmp\wrx1.do
test\tmp\ASC_test2
test\tmp\ASC_test3
test\tmp\ASC_test4
test\tmp\wave.do
test\tmp\wave1.do
test\tmp\wave2.do
test\tmp\wave4.do
test\tmp\ASC_test1
test\tmp\wrx.txt
test\tmp\wrx4.do
test\tmp\ASC4
test\tmp\sARM_tb\asm\ASC
test\tmp\sARM_tb\asm\BIN2ASC.EXE
test\tmp\sARM_tb\asm\add64\add64.apj
test\tmp\sARM_tb\asm\add64\add64.jpg
test\tmp\sARM_tb\asm\add64\add64.o
test\tmp\sARM_tb\asm\add64\add64.txt
test\tmp\sARM_tb\asm\add64\add64.txt.bak
test\tmp\sARM_tb\asm\add64\add64_SDT.jpg
test\tmp\sARM_tb\asm\add64\ASC
test\tmp\sARM_tb\asm\add64\ASC_test1
test\tmp\sARM_tb\asm\add64
test\tmp\sARM_tb\asm\adrlabel\adrlabel.apj
test\tmp\sARM_tb\asm\adrlabel\adrlabel.o
test\tmp\sARM_tb\asm\adrlabel\adrlabel.s
test\tmp\sARM_tb\asm\adrlabel\ASC
test\tmp\sARM_tb\asm\adrlabel
test\tmp\sARM_tb\asm\armex\armex.apj
test\tmp\sARM_tb\asm\armex\armex.o
test\tmp\sARM_tb\asm\armex\armex.s
test\tmp\sARM_tb\asm\armex\ASC
test\tmp\sARM_tb\asm\armex
test\tmp\sARM_tb\asm\fft\fft
test\tmp\sARM_tb\asm\fft\int_fft.c
test\tmp\sARM_tb\asm\fft\int_fft.c.bak
test\tmp\sARM_tb\asm\fft\project1.apj
test\tmp\sARM_tb\asm\fft
test\tmp\sARM_tb\asm\jump\ASC
test\tmp\sARM_tb\asm\jump\jump.apj
test\tmp\sARM_tb\asm\jump\jump.o
test\tmp\sARM_tb\asm\jump\jump.s
test\tmp\sARM_tb\asm\jump
test\tmp\sARM_tb\asm\ldrlabel\ASC
test\tmp\sARM_tb\asm\ldrlabel\ldrlabel.apj
test\tmp\sARM_tb\asm\ldrlabel\ldrlabel.jpg
test\tmp\sARM_tb\asm\ldrlabel\ldrlabel.o
test\tmp\sARM_tb\asm\ldrlabel\ldrlabel.s
test\tmp\sARM_tb\asm\ldrlabel\ldrlabel_SDT.jpg
test\tmp\sARM_tb\asm\ldrlabel
test\tmp\sARM_tb\asm\loadcon\ASC
test\tmp\sARM_tb\asm\loadcon\loadcon.apj
test\tmp\sARM_tb\asm\loadcon\loadcon.jpg
test\tmp\sARM_tb\asm\loadcon\loadcon.o
test\tmp\sARM_tb\asm\loadcon\loadcon.s
test\tmp\sARM_tb\asm\loadcon\loadcon_SDT.jpg
test\tmp\sARM_tb\asm\loadcon
test\tmp\sARM_tb\asm\mla\ASC
test\tmp\sARM_tb\asm\mla\mla.o
test\tmp\sARM_tb\asm\mla\mla.s
test\tmp\sARM_tb\asm\mla\mla1.jpg
test\tmp\sARM_tb\asm\mla\mla2.jpg
test\tmp\sARM_tb\asm\mla\mla3.jpg
test\tmp\sARM_tb\asm\mla\project1.apj
test\tmp\sARM_tb\asm\mla
test\tmp\sARM_tb\asm\mul\ASC
test\tmp\sARM_tb\asm\mul\mul.o
test\tmp\sARM_tb\asm\mul\mul.s
test\tmp\sARM_tb\asm\mul\mul1.jpg
test\tmp\sARM_tb\asm\mul\mul2.jpg
test\tmp\sARM_tb\asm\mul\mul3.jpg
test\tmp\sARM_tb\asm\mul\project1.apj
test\tmp\sARM_tb\asm\mul
test\tmp\sARM_tb\asm\mul64\mul64.apj
test\tmp\sARM_tb\asm\mul64\mul64.s
test\tmp\sARM_tb\asm\mul64
test\tmp\sARM_tb\asm\strcopy\ASC
test\tmp\sARM_tb\asm\strcopy\strcopy.apj
test\tmp\sARM_tb\asm\strcopy\strcopy.jpg
test\tmp\sARM_tb\asm\strcopy\strcopy.o
test\tmp\sARM_tb\asm\strcopy\strcopy.s
test\tmp\sARM_tb\asm\strcopy\strcopy_SDT.jpg
test\tmp\sARM_tb\asm\strcopy
test\tmp\sARM_tb\asm
test\tmp\sARM_tb\bin2asc\ASC
test\tmp\sARM_tb\bin2asc\bin2asc.cpp
test\tmp\sARM_tb\bin2asc\bin2asc.cpp.bak
test\tmp\sARM_tb\bin2asc\BIN2ASC.EXE
test\tmp\sARM_tb\bin2asc
test\tmp\sARM_tb
test\tmp\bak\Arbitrator.v
test\tmp\bak\BusTransfer.v
test\tmp\bak\CacheMemory.v
test\tmp\bak\CAM.v
test\tmp\bak\datac2.v
test\tmp\bak\DataCacheController.v
test\tmp\bak\DataCacheMemory.v
test\tmp\bak\Def_ComponentEntry.v
test\tmp\bak\InstructionCacheController.v
test\tmp\bak\InstructionPreFetch.v
test\tmp\bak\MemoryController.v
test\tmp\bak\MemoryMux.v
test\tmp\bak\nnARM.prog
test\tmp\bak\nnARM.v
test\tmp\bak\nnARM11.v
test\tmp\bak\README.doc
test\tmp\bak\scr.cmd
test\tmp\bak\scr1.cmd
test\tmp\bak\scr3.cmd
test\tmp\bak\System.v
test\tmp\bak\tb_Adder.v
test\tmp\bak\tb_BarrelShift.v
test\tmp\bak\tb_complementary.v
test\tmp\bak\tb_Decoder_ARM.v
test\tmp\bak\tb_IF.v
test\tmp\bak\tb_InstructionPreFetch.v
test\tmp\bak\tb_RegisterFile.v
test\tmp\bak\tb_system_fft.v
test\tmp\bak\tb_tomasulo.v
test\tmp\bak\TestInstruction.v
test\tmp\bak\wARM.doc
test\tmp\bak
test\tmp
test\wrxsim\wave42.do
test\wrxsim\wave11.do
test\wrxsim\仿真分析41.txt
test\wrxsim\仿真分析43.txt
test\wrxsim\wave43.do
test\wrxsim\仿真分析42.txt
test\wrxsim\仿真分析44.txt
test\wrxsim\wave44.do
test\wrxsim\仿真分析12.txt
test\wrxsim\wave11.jpg
test\wrxsim\wave12.jpg
test\wrxsim\wave13.jpg
test\wrxsim\仿真分析32.txt
test\wrxsim\仿真分析11.txt
test\wrxsim\wave14.jpg
test\wrxsim\wave15.jpg
test\wrxsim\wave16.jpg
test\wrxsim\wave21.jpg
test\wrxsim\wave22.jpg
test\wrxsim\wave31.jpg
test\wrxsim\wave41.jpg
test\wrxsim\wave42.jpg
test\wrxsim\wave43.jpg
test\wrxsim\wave44.jpg
test\wrxsim\仿真分析13.txt
test\wrxsim\仿真分析15.txt
test\wrxsim\仿真分析14.txt
test\wrxsim\仿真分析16.txt
test\wrxsim\wave12.do
test\wrxsim\wave13.do
test\wrxsim\wave14.do
test\wrxsim\wave15.do
test\wrxsim\wave16.do
test\wrxsim\wrx.do
test\wrxsim\wave21.do
test\wrxsim\仿真分析21.txt
test\wrxsim\wave22.do
test\wrxsim\仿真分析22.txt
test\wrxsim\wave31.do
test\wrxsim\仿真分析31.txt
test\wrxsim\wave41.do
test\wrxsim
test\work\_info
test\work\w_tb\_primary.vhd
test\work\w_tb\verilog.asm
test\work\w_tb\_primary.dat
test\work\w_tb
test\work\w@a@r@m1\_primary.vhd
test\work\w@a@r@m1\verilog.asm
test\work\w@a@r@m1\_primary.dat
test\work\w@a@r@m1
test\work\@mem_ctrl\_primary.vhd
test\work\@mem_ctrl\verilog.asm
test\work\@mem_ctrl\_primary.dat
test\work\@mem_ctrl
test\work\@d_@bus2@core\_primary.vhd
test\work\@d_@bus2@core\verilog.asm
test\work\@d_@bus2@core\_primary.dat
test\work\@d_@bus2@core
test\work\@i_@bus2@core\_primary.vhd
test\work\@i_@bus2@core\verilog.asm
test\work\@i_@bus2@core\_primary.dat
test\work\@i_@bus2@core
test\work\@arbiter_@w@b\_primary.vhd
test\work\@arbiter_@w@b\verilog.asm
test\work\@arbiter_@w@b\_primary.dat
test\work\@arbiter_@w@b
test\work\w@a@r@m@core\_primary.vhd
test\work\w@a@r@m@core\verilog.asm
test\work\w@a@r@m@core\_primary.dat
test\work\w@a@r@m@core
test\work\@p@s@r_new\_primary.vhd
test\work\@p@s@r_new\verilog.asm
test\work\@p@s@r_new\_primary.dat
test\work\@p@s@r_new
test\work\@i@p\_primary.vhd
test\work\@i@p\verilog.asm
test\work\@i@p\_primary.dat
test\work\@i@p
test\work\@i@t\_primary.vhd
test\work\@i@t\verilog.asm
test\work\@i@t\_primary.dat
test\work\@i@t
test\work\thumb_2_nnarm\_primary.vhd
test\work\thumb_2_nnarm\verilog.asm
test\work\thumb_2_nnarm\_primary.dat
test\work\thumb_2_nnarm
test\work\@p@s@r\_primary.vhd
test\work\@p@s@r\verilog.asm
test\work\@p@s@r\_primary.dat
test\work\@p@s@r
test\work\@can@go@gen\_primary.vhd
test\work\@can@go@gen\verilog.asm
test\work\@can@go@gen\_primary.dat
test\work\@can@go@gen
test\work\@r@f\_primary.vhd
test\work\@r@f\verilog.asm
test\work\@r@f\_primary.dat
test\work\@r@f
test\work\@m@e@m\_primary.vhd
test\work\@m@e@m\verilog.asm
test\work\@m@e@m\_primary.dat
test\work\@m@e@m
test\work\@a@l@ucc\_primary.vhd
test\work\@a@l@ucc\verilog.asm
test\work\@a@l@ucc\_primary.dat
test\work\@a@l@ucc
test\work\@barrel@shift\_primary.vhd
test\work\@barrel@shift\verilog.asm
test\work\@barrel@shift\_primary.dat
test\work\@barrel@shift
test\work\@adder\_primary.vhd
test\work\@adder\verilog.asm
test\work\@adder\_primary.dat
test\work\@adder
test\work\@comp\_primary.vhd
test\work\@comp\verilog.asm
test\work\@comp\_primary.dat
test\work\@comp
test\work\@a@l@uss\_primary.vhd
test\work\@a@l@uss\verilog.asm
test\work\@a@l@uss\_primary.dat
test\work\@a@l@uss
test\work\@i@d\_primary.vhd
test\work\@i@d\verilog.asm
test\work\@i@d\_primary.dat
test\work\@i@d
test\work\@i@f\_primary.vhd
test\work\@i@f\verilog.asm
test\work\@i@f\_primary.dat
test\work\@i@f
test\work
test