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VHDL-FPGA-Verilog list
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new
Downloaded:0
vhdl code aes algorithm newly modified
Date
: 2026-01-12
Size
: 185kb
User
:
gopalakirshnan
soft_demapper
Downloaded:0
this will implement soft demapper in verilog
Date
: 2026-01-12
Size
: 2kb
User
:
ashwanth
verilog-code-FOR-COMPARATOR--TFF-AND-BCD-TO-7SSD.
Downloaded:0
// File : 4 Bit Comparator design using behavior modeling style.v
Date
: 2026-01-12
Size
: 2kb
User
:
dhishna
Digital-Picture-Frame
Downloaded:1
Digital Photo Frame. Columbia University CSEE 4840 Course Design
Date
: 2026-01-12
Size
: 767kb
User
:
孙江波
Embedded-Image-Capture
Downloaded:0
Embedded image acquisition. Columbia University CSEE 4840 Course Design
Date
: 2026-01-12
Size
: 5mb
User
:
孙江波
Internet-radio-broadcaster
Downloaded:0
Network audio transmission. Columbia University CSEE 4840 Course Design
Date
: 2026-01-12
Size
: 1.27mb
User
:
孙江波
Real-time-Pitch-Detector
Downloaded:0
Real-time pitch detection system. Columbia University CSEE 4840 Course Design
Date
: 2026-01-12
Size
: 386kb
User
:
孙江波
Voip-SIP-Telephone
Downloaded:0
Internet telephony. Columbia University CSEE 4840 Course Design
Date
: 2026-01-12
Size
: 998kb
User
:
孙江波
RSR
Downloaded:0
Automatic aiming and missile launchers robots. Columbia University CSEE 4840 Course Design
Date
: 2026-01-12
Size
: 4.41mb
User
:
孙江波
mcu8051
Downloaded:0
An implementation MCU51 processor complete VHDL source code, including testbench
Date
: 2026-01-12
Size
: 216kb
User
:
Chen Haijun
PLI-example
Downloaded:0
PLI is the specification to perform interface between C and HDL language. This example give a c function called by verilog!
Date
: 2026-01-12
Size
: 297kb
User
:
hanyu
FPGA-implementation-of-CORDIC
Downloaded:0
The current trend back toward hardware intensive signal processing has uncovered a relative lack of understanding of hardware signal processing architectures.Many hardware efficient algorithms exist,but these are general
Date
: 2026-01-12
Size
: 117kb
User
:
可难
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