VHDL-FPGA-Verilog List Page 858

VHDL-FPGA-Verilog list

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fft256 Downloaded：0: Use FPGA ip core to achieve the 256-point FFT conversion with vhdL language.
Date : 2025-07-27 Size : 919kb User : 贺风
ADCS5451A_Sample Downloaded：0: Using verilog language to achieve ADCS5451 AD converter chip control and data read.
Date : 2025-07-27 Size : 1kb User : 贺风
arbiter-design-and-verification Downloaded：0: design and verification of arbiter
Date : 2025-07-27 Size : 4kb User : satish devrari
fat32_2G Downloaded：0: DE2 development board SD card related design, interested can download Ha!
Date : 2025-07-27 Size : 19.62mb User : ailsa
FPGA_QPSK_EXP Downloaded：0: Quartus simulation module written QPSK demodulation hardware emulation for various functional modules using VHDL language for communications engineering professionals use
Date : 2025-07-27 Size : 332kb User : paipai
zuoyepaoma2 Downloaded：0: Marquee FPGA-based design can achieve an independent running lights, two lights Lianpao, intermittent run, run across two lights running lights in the form of custom. quartus software pro-test is available, I have writte
Date : 2025-07-27 Size : 1kb User : 司维
fifo_env Downloaded：0: for synchronization when we are dealing with 2 different clock domain
Date : 2025-07-27 Size : 1.92mb User : joheb
huxi Downloaded：0: VHDL-based design in four different frequencies breathing light, breathing frequency was 0.1Hz, 0.2Hz, 0.4Hz, 0.8Hz breathing light principle: the use PWM to control the brightness led the wave, the source code is availa
Date : 2025-07-27 Size : 1kb User : 司维
daojishi Downloaded：0: 60S-based VHDL, countdown, countdown start time can be set, reset the countdown, countdown to the end of the LED will blink, buzzer alarm, quartus software pro-test available.
Date : 2025-07-27 Size : 1kb User : 司维
huxideng Downloaded：0: VHDL-based design breathing light can be set to four frequencies were 0.1, 0.2,0.4 0.5MHZ, quartus software pro-test available
Date : 2025-07-27 Size : 1kb User : 司维
zuoye60 Downloaded：0: 60S countdown VHDL-based design, with a digital display, the countdown is completed after the buzzer alarm
Date : 2025-07-27 Size : 1kb User : 司维
verilog Downloaded：0: " Verilog_ Digital System Design Course" (Second Edition) Questions answers. Rar
Date : 2025-07-27 Size : 529kb User : 李群

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