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VHDL-FPGA-Verilog list
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bcd_to_dec
Downloaded:0
VHDL code for converting BCD to Decimal
Date
: 2025-05-16
Size
: 157kb
User
:
spiegel
State_machine_1
Downloaded:0
VHdL code to implement simple state machine
Date
: 2025-05-16
Size
: 138kb
User
:
spiegel
tt
Downloaded:0
VHDL Implementation of decade counter
Date
: 2025-05-16
Size
: 264kb
User
:
spiegel
2_4decoder
Downloaded:0
Three styles of VHDL code to quickly establish the concept and structure of different style description languages
Date
: 2025-05-16
Size
: 567kb
User
:
名之联
cnt8updown
Downloaded:0
an 8-bit up and down synchronous counter in VHDL with the following features: (1) The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered (three-state). (2) The counter i
Date
: 2025-05-16
Size
: 991kb
User
:
名之联
uut_3
Downloaded:0
VHDL designed FIFO classic structure functions in detail please refer to
Date
: 2025-05-16
Size
: 820kb
User
:
名之联
A4_Clock
Downloaded:0
clock program based on Cyclone4 of Altera
Date
: 2025-05-16
Size
: 3.37mb
User
:
DSP新手
lab2B(4)LFSR
Downloaded:0
Implementation of generation random 4 bits code in verilog
Date
: 2025-05-16
Size
: 1kb
User
:
电聪骑风
371231d
Downloaded:0
file information such as datasheet
Date
: 2025-05-16
Size
: 262kb
User
:
keyurm
372468a
Downloaded:0
fpga documentation regarding something
Date
: 2025-05-16
Size
: 236kb
User
:
keyurm
374566d
Downloaded:0
html documents for programming
Date
: 2025-05-16
Size
: 526kb
User
:
keyurm
axi_slave
Downloaded:0
The slave part of Axi in the AMBA bus, slave. implemented with Verilog
Date
: 2025-05-16
Size
: 1kb
User
:
过客3944
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