VHDL-FPGA-Verilog List Page 816

VHDL-FPGA-Verilog list

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FPGADE270CACULATOR Downloaded：0: This article describes a simple calculator design that uses a field programmable logic device FPGA design and VHDL language based on arithmetic functions, and decimal display on LCD1602.
Date : 2025-07-22 Size : 3.24mb User : 南宫崔浩
dianti Downloaded：0: 6-story elevator design, using vhdl prepared, able to lift function experiments
Date : 2025-07-22 Size : 4kb User : fandaowei
traffic Downloaded：0: Traffic lights display, time display, to the point when the traffic lights will be converted
Date : 2025-07-22 Size : 1.68mb User : Amy-nmw
Example-b8-6 Downloaded：0: Synplify Pro comprehensive process simulation (note: this example provides two Verilog and VHDL language version at the same time, please choose the different readers according to the habits of the source code.
Date : 2025-07-22 Size : 121kb User : 波罗的海
Example-b8-5 Downloaded：0: Learn the basics of using VCD files,Four state VCD file, change the parameters between 0/1/X/Z no signal strength information
Date : 2025-07-22 Size : 11kb User : 波罗的海
AD_TLC549-analog-signal-acquisition Downloaded：0: AD_TLC549 analog signal acquisition AD_TLC549 analog signal acquisition
Date : 2025-07-22 Size : 1.76mb User : 李雅哲
Example-b8-3 Downloaded：0: DO learn how to use basic file simulation method, according to the syntax of the command or ModelSim provides Tcl/Tk language will flow simulation simulation Cmd command sequence written to the macro file extension "do"
Date : 2025-07-22 Size : 12kb User : 波罗的海
shift-register Downloaded：0: Design and Simulation of the shift register are both hosting the data shift register, and can make the data shift circuit. The so-called shift function, is registered in the data circuit, a pulse may be shifted under the
Date : 2025-07-22 Size : 3kb User : Zero Liang
fifo Downloaded：0: A classic instance of fifo Verilog project, I believe there will be some help for beginners.
Date : 2025-07-22 Size : 1kb User : Carl
timer Downloaded：0: A simple stopwatch based on VHDL, including key debounce module, digital decoder, timers and other modules. Directly applicable to basys2 and nexys3 two development boards. After changing the ucf file applicable to other
Date : 2025-07-22 Size : 16kb User : 潘健森
fifo2 Downloaded：0: Asynchronous fifo FIFO for buffering data, using verilog HDL written in quartus II test through, modelsim simulation
Date : 2025-07-22 Size : 4kb User : T~T
audioloopback Downloaded：0: Verilog program for running a audio loopback system for AC97 codec.
Date : 2025-07-22 Size : 3kb User : Nitesh

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