VHDL-FPGA-Verilog List Page 670

VHDL-FPGA-Verilog list

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div Downloaded：0: frequency dividing circuit
Date : 2025-12-31 Size : 211kb User : 舒占军
ROM Downloaded：0: read only memory
Date : 2025-12-31 Size : 4.18mb User : 舒占军
stack Downloaded：0: fist in last out
Date : 2025-12-31 Size : 4.3mb User : 舒占军
KEY_LED_FPGA_VerilogHDL Downloaded：0: FPGA buttons and LED, Verilog HDL code
Date : 2025-12-31 Size : 118kb User : 贺炜
LCD1602_FPGA_VerilogHDL Downloaded：0: FPGA LCD1602 display, Verilog HDL code
Date : 2025-12-31 Size : 279kb User : 贺炜
LCD12864_FPGA_VerilogHDL Downloaded：0: FPGA LCD12864, Verilog HDL code
Date : 2025-12-31 Size : 271kb User : 贺炜
UART_FPGA_VerilogHDL Downloaded：0: FPGA RS232 serial communication, Verilog HDL code
Date : 2025-12-31 Size : 254kb User : 贺炜
J_TAP-state-transitions-described Downloaded：0: J_TAP state transitions described in the program, J_tap using VHDL language to describe the state transitions can be directly burned EDA hardware implementation.
Date : 2025-12-31 Size : 1kb User : 閮戝竻
sp605_IBERT_rdf0036_13.3_c Downloaded：2: This file is an example top wrapper for the ibert design with the required clock buffers. User logic can be instantiated in this wrapper along with the ibert design.
Date : 2025-12-31 Size : 1.26mb User : 李万泉
0-example_test_board_x Downloaded：0: This Board consists of 5 LED, where D1 is the onboard 3.3V indicator D2-D5 FPGA IO mouth control power on after-burning program, D1 point light indicates that power is good the remaining 4 in turn LED light indicate that
Date : 2025-12-31 Size : 3.37mb User : 李万泉
12061226project8 Downloaded：0: cpu simulator
Date : 2025-12-31 Size : 45kb User : leon
T01_UART_CORE Downloaded：0: Verilog implementation of the UART serial port to read and write control nuclear parametric check, clock setting, complete project (Xilinx), including documentation, source code and so on. For learning reference, hope yo
Date : 2025-12-31 Size : 414kb User : FEIFEI

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