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VHDL-FPGA-Verilog list
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Serial communication with VHDL source code written in the fpga verified
Date : 2025-08-31 Size : 3kb User : 王三木

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Writing VHDL design of traffic lights, suitable for beginners reference
Date : 2025-08-31 Size : 31kb User : 王三木

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Using VHDL source code written in Chinese characters scrolling display can be used as reference for beginners
Date : 2025-08-31 Size : 30kb User : 王三木

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Compare FPGA source code written for beginners reference, compiled by ALTERA s QUARTUS 11.0
Date : 2025-08-31 Size : 306kb User : whq

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Principle and Implementation clock divider, counting and addition and subtraction frequency hopping mode changes in real time, through the LCD display panel show Nano experiments. Counting frequency, subtraction selectio
Date : 2025-08-31 Size : 799kb User : 范鹏

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Basic features: 1. Eight Responder, while for eight contestants, numbered 1-8. Each player with an answer button and LED lights, when the players pressed their lights. 2. to host a control switch, reset the system to ach
Date : 2025-08-31 Size : 812kb User : 范鹏

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DE2 70 development board driver digital tube, and designed a clock counter, clock count, minutes, seconds.
Date : 2025-08-31 Size : 841kb User : 李桐

Verilog HDL CY7C68013 and FPGA implementation of the interface
Date : 2025-08-31 Size : 172kb User : 孙超

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one time mode continue mode
Date : 2025-08-31 Size : 3kb User : liangfengbo

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Filter source code, circuit lab take the necessary source code, very easy to use
Date : 2025-08-31 Size : 2kb User : 田飞龙

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Laboratory test code circuit filter take the necessary source code, very easy to use
Date : 2025-08-31 Size : 29kb User : 田飞龙

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verilog Implementation of Mean filter to implement in FPGA
Date : 2025-08-31 Size : 13kb User : chaitu
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