VHDL-FPGA-Verilog List Page 615

VHDL-FPGA-Verilog list

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sleep_wake-up Downloaded：0: SLEEP WAKE UP FOR CSR CPU
Date : 2025-08-31 Size : 1kb User : 郑自汉
e2prom_w_r Downloaded：0: test bench of EEPROM write and read for FPGA
Date : 2025-08-31 Size : 80kb User : Johnny
i2cslave_verilog Downloaded：0: I2C slave.
Date : 2025-08-31 Size : 2kb User : 余军
relay_test Downloaded：0: Simple relay trigger
Date : 2025-08-31 Size : 340kb User : danny
DE4_230_DDR2_UniPHY_QSYS Downloaded：0: DE4 series development board on the DDR2 in the example of Qsys system, has a certain reference value,.
Date : 2025-08-31 Size : 8.32mb User : hcl
hdl Downloaded：0: spi verilog ad9628
Date : 2025-08-31 Size : 5kb User : dragonlee
bcd27seg Downloaded：0: Tranfer BCD to 7 Segs
Date : 2025-08-31 Size : 24kb User : MrTranLam
paobiao Downloaded：0: Stopwatch functions implemented in the FPGA, with the counting process milliseconds, microseconds to seconds, can be simulated in the development board.
Date : 2025-08-31 Size : 661kb User : 小璐璐
uart_io_test Downloaded：0: verilog in the PC UART communication protocols, seen people say well, has verified the accuracy, very good code.
Date : 2025-08-31 Size : 554kb User : 小璐璐
SI4432_TX_192 Downloaded：0: FPGA-based wireless passthrough module SI4432 VERILOG engineering, testing available
Date : 2025-08-31 Size : 3.4mb User : 王楠
SI4432_RX_192 Downloaded：0: FPGA-based wireless passthrough module SI4432 VERILOG engineering, testing available
Date : 2025-08-31 Size : 5.3mb User : 王楠
led Downloaded：0: Water lamp, the clock control, each time display different colors, a total of 32 colors
Date : 2025-08-31 Size : 1kb User : Mr.Do

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