VHDL-FPGA-Verilog List Page 433

VHDL-FPGA-Verilog list

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AX301_jtag_uart_test Downloaded：0: AX301 development board,JTAG port driver and debug experiment code
Date : 2025-06-16 Size : 3kb User : 张天奇
AX301_Real_time_clock_test Downloaded：0: AX301 FPGA development board,Real time clock test code
Date : 2025-06-16 Size : 3kb User : 张天奇
sdram_learn_8bit Downloaded：0: learning information for beginning learners
Date : 2025-06-16 Size : 3.81mb User : 李梦
a_vhd_16550_uart Downloaded：0: Using the UART core is the similar to using the standard 16550 UART, expect that the FIFO’s are always enabled, and there is no sticky parity.
Date : 2025-06-16 Size : 128kb User : 丁一
fpu_double Downloaded：0: The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to me
Date : 2025-06-16 Size : 239kb User : 丁一
Divide Downloaded：0: This a divider verilog code
Date : 2025-06-16 Size : 1kb User : Kumar
ALU Downloaded：0: This MIPS ALU verilog code
Date : 2025-06-16 Size : 3kb User : Kumar
Mux4 Downloaded：0: This Mux4 verilog code.
Date : 2025-06-16 Size : 1kb User : Kumar
Control Downloaded：0: Datapath Controller verilog code
Date : 2025-06-16 Size : 4kb User : Kumar
MemControl Downloaded：1: Memory Controller verilog code.
Date : 2025-06-16 Size : 3kb User : Kumar
FPGA-Source-Code_VHDL Downloaded：0: source code of FX2LP_SLAVE_FIFO CONTROLLER S
Date : 2025-06-16 Size : 1.12mb User : 赵
hbfir Downloaded：0: 31order,halfband fir ,multi-channel
Date : 2025-06-16 Size : 4kb User : 马乾

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