VHDL-FPGA-Verilog List Page 431

VHDL-FPGA-Verilog list

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uart Downloaded：0: UART serial communication, 50M crystal, 256,000 baud rate ( 9600-256000 optional), 8 data bits, 1 start, an end, no parity bit, stable transmission test.
Date : 2025-06-16 Size : 3.03mb User : 李亚文
alu Downloaded：0: this a alu code.
Date : 2025-06-16 Size : 1kb User : 胡英鹏
Booth2_16 Downloaded：0: 16 bit booth order 2 with symbolic multipliers and related test procedures
Date : 2025-06-16 Size : 1kb User : 胡英鹏
sp6ex16 Downloaded：0: The document is based on xilinx spartan 6 chip implements the source program uart communication
Date : 2025-06-16 Size : 2.69mb User : liu
sp6ex18 Downloaded：0: Based on the on-chip RAM for continuous reading and writing test cases for Verilog HDL
Date : 2025-06-16 Size : 4.85mb User : liu
LED_PATTERN Downloaded：0: I HAVE NOW UPLOADED A DESIGN IMPLEMENTING DIFFERENT LED PATTERN ON FPGA BASED BOARD.IN THIS CODE BOTH SEVEN SEGMENT AND LED DISPLAY USED AT THE SAME TIME
Date : 2025-06-16 Size : 455kb User : ANMOL GUPTA
OOK_TEST Downloaded：0: The code is for 2ASK modulation and demodulation.
Date : 2025-06-16 Size : 2.82mb User : luo
LCDcontrol Downloaded：1: verilog code for t6963 240128 lcd
Date : 2025-06-16 Size : 2.21mb User : 孙虎
LCDTEXT Downloaded：0: another verilog code for t6963 lcd
Date : 2025-06-16 Size : 1.44mb User : 孙虎
project_2 Downloaded：0: Realized FPGA-based FFT transform, starting with the most basic 32-bit binary floating-point addition and subtraction multiplication module, a FFT module assembly. At the same time simulation files in 32-bit floating-poi
Date : 2025-06-16 Size : 2.99mb User : 韦壮焜
Papilio Downloaded：0: demonstrate the sdram usuage
Date : 2025-06-16 Size : 32kb User : jamesri
and_gate Downloaded：0: verilog code for and gate
Date : 2025-06-16 Size : 2kb User : Nilendu Ghosal

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