VHDL-FPGA-Verilog List Page 4277

VHDL-FPGA-Verilog list

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vh Downloaded：0: useful VHDL source code
Date : 2025-08-12 Size : 577kb User : 王新
VHDL语言基本数学运算库 Downloaded：0: VHDL basic arithmetic library
Date : 2025-08-12 Size : 242kb User : 崔广辉
Adnence_add8 Downloaded：0: the VHDL-ahead Adder
Date : 2025-08-12 Size : 42kb User : 安鹏洲
usb1.1_Verilog Downloaded：1: USB1.1 IP core for device control, written with hardware describing language of Verilog.
Date : 2025-08-12 Size : 128kb User : 李恒
占空比1：1的通用分频模块 Downloaded：0: 1:1 generic-frequency module
Date : 2025-08-12 Size : 1kb User : 陈平
superSPI Downloaded：0: with AHDL prepared MAXPULS development. Communications from external clock rate and restriction on the number of data bytes.
Date : 2025-08-12 Size : 1kb User : 陈瑞
UART 源码 (lattice version) Downloaded：0: UART source (lattice version)
Date : 2025-08-12 Size : 85kb User : 了类似
VHDL Programing Downloaded：0: VHDL Programing
Date : 2025-08-12 Size : 1.7mb User : 陈凯
uart_vhdl_xilinx Downloaded：0: xilinx simulator programme of serial port
Date : 2025-08-12 Size : 9kb User : 赵兴涛
uart_vhdl_lattice Downloaded：0: serial port simulated programme of lattice
Date : 2025-08-12 Size : 42kb User : 赵兴涛
VHDL源代码1 Downloaded：0: VHDL source code
Date : 2025-08-12 Size : 4kb User : 宋涛
VHDL源代码2 Downloaded：0: and VHDL source code
Date : 2025-08-12 Size : 5kb User : 宋涛

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