VHDL-FPGA-Verilog List Page 4270

VHDL-FPGA-Verilog list

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idec Downloaded：0: 2. You may use this core in any way, be it academic, commercial, or-- military. Modified or not.
Date : 2025-08-12 Size : 2kb User : 江浩
regs Downloaded：0: 3. Distribution of this core must be free of charge. Charging is-- allowed only for value added services. Value added services-- would include copying fees, modifications, customizations, and-- inclusion in other product
Date : 2025-08-12 Size : 2kb User : 江浩
dram Downloaded：0: 4. If a modified source code is distributed, the original unmodified-- source code must also be included (or a link to the Free IP web-- site). In the modified source code there must be clear-- identification of the modi
Date : 2025-08-12 Size : 1kb User : 江浩
1032yiwei_new Downloaded：0: CPLD LATTICE1032 test model code
Date : 2025-08-12 Size : 2kb User : 冯达
FIR低通滤波器部分模块 Downloaded：0: This a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.
Date : 2025-08-12 Size : 5kb User : 吴健宇
数字电子钟 Downloaded：0: digital electronic clock this digital electronic clock with functions include : 1. Time, hours, minutes and seconds display; 2. 12 hours with 24 hours of conversion; 3. On the afternoon show; 4. Right hours, minutes, and
Date : 2025-08-12 Size : 7kb User : 吴健宇
数字锁相环 Downloaded：0: digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate lin
Date : 2025-08-12 Size : 122kb User : 于洪彪
NO_2_ColorLight Downloaded：0: this is the Lantern example VHDL procedures inside covers 48 species of Carnival changes adopted maxplus certification, and the plane through experiments
Date : 2025-08-12 Size : 101kb User : 何蓥
flash接口控制_verilog Downloaded：0: flash interface controller VHDL and Verilog source code and procedures Testbench
Date : 2025-08-12 Size : 850kb User : 李楠
印制线路板设计经验点滴 Downloaded：0: Printed Circuit Board Design Experience
Date : 2025-08-12 Size : 7kb User : 张军
消抖通用函数XIAOPRO： Downloaded：0: EDA very important small procedures to ensure that key reliability and prevent jitter error signal generated, the external input signal must use this function Consumers shiver
Date : 2025-08-12 Size : 2kb User : 李培
译码 Downloaded：0: EDA common dual LED display decoding procedure will be four binary decoding for seven LED7 spaces corresponding to the input signal circuits
Date : 2025-08-12 Size : 2kb User : 李培

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