VHDL-FPGA-Verilog List Page 4152

VHDL-FPGA-Verilog list

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decdor_38 Downloaded：0: VHDL addendum to the encoder, with a variety of functions and warm sense of hope do share with you ~!
Date : 2025-05-19 Size : 1kb User : leochen
licheng Downloaded：0: Verilog the procedures for scanning into the keyboard, then were sent to 51 micro-processing procedures.
Date : 2025-05-19 Size : 250kb User : 江
taxi_counter Downloaded：0: a taxi prepared by the accounting device, starting six yuan or 2 km, then every half kilometer or 0.8 yuan, stopping to wait for every 2.5 minutes or 0.8 yuan. Through simulation, but not download to test CPLD
Date : 2025-05-19 Size : 237kb User : 尚方喆
chipscope_vhdl_fpga_xilinx Downloaded：0: chipscope directory and on-line debugging of FPGA methodology aaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa
Date : 2025-05-19 Size : 373kb User : 张红静
RAM_VHDL_34 Downloaded：0: RAM's VHDL description RAM's VHDL description RAM's VH DL described in VHDL's RAM
Date : 2025-05-19 Size : 5kb User :
cordic_1-0 Downloaded：0: Cordic algorithms to achieve another C is a sample that can be used TubroC, etc. to see
Date : 2025-05-19 Size : 9kb User : 郝晋
magnitude Downloaded：0: Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algor
Date : 2025-05-19 Size : 12kb User : 郝晋
index Downloaded：0: achieve long strings of binary arithmetic right side of the operation. Want a little reference value. Direct operations and opinions 1,10. . . Thank you, `
Date : 2025-05-19 Size : 16kb User : 杨海平
VHDLchufaqi Downloaded：0: MAXPLUS2 prepare themselves VHDL four Divider
Date : 2025-05-19 Size : 126kb User : 刘建
Quartus_vhdl Downloaded：0: QUARTUS used by the compiler, and other precision frequency, I am wrong. But there are several warning (not affect design). I graduated from the design ah! ! !
Date : 2025-05-19 Size : 43kb User : 刘刚
redandyellow Downloaded：0: traffic lights, traffic lights crossroads VHDL procedures, absolutely available
Date : 2025-05-19 Size : 48kb User :
b8bit_adder Downloaded：0: eight of the adder design, four hours to complete the project, using the Quartus II software.
Date : 2025-05-19 Size : 508kb User : jk

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