VHDL-FPGA-Verilog List Page 4137

VHDL-FPGA-Verilog list

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foudiv Downloaded：0: Can be achieved for any arbitrary waveform at frequency, frequency addition and subtraction through the keys to achieve.
Date : 2025-05-20 Size : 212kb User : 莱密
qiangdaqi(auto) Downloaded：0: Using hardware description language verilog hdl people realize Answer feature, have timing, scoring and alarm functions.
Date : 2025-05-20 Size : 260kb User : 杨操
D0324stimer Downloaded：0: Basketball 24s timer, the components are simple, the function is complicated. Meet the small timing needs.
Date : 2025-05-20 Size : 179kb User : 杨操
ps2_keyboard Downloaded：0: PS2 keyboard to control the content of the experimental procedure is used EDK build a simple system and add custom peripherals (a ps2 keyboard controller) when the keyboard is pressed the corresponding button will scan c
Date : 2025-05-20 Size : 5kb User : 刘安
PN-arraycheck Downloaded：0: QuartusII use in AHDL language, the first PN generator designed to generate a data stream 11 throughout the cycle has an effective data = 2047 re-designing the state machine used to detect the serial data stream in seque
Date : 2025-05-20 Size : 377kb User : 戴振华
modelsim6.0 Downloaded：0: ModelSim for use of how to operate and use and installation of how to install
Date : 2025-05-20 Size : 379kb User : kkk
leon3-altera-ep2s60-ddr Downloaded：0: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not
Date : 2025-05-20 Size : 112kb User :
spi Downloaded：0: SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
Date : 2025-05-20 Size : 64kb User : 阿飞
quartusII7.1crack Downloaded：0: quartus_II_7.1
Date : 2025-05-20 Size : 851kb User : li
DspBuilder6.0_License Downloaded：0: DspBulider6.0
Date : 2025-05-20 Size : 456kb User : li
S3Demo Downloaded：0: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The sev
Date : 2025-05-20 Size : 714kb User : Roy Hsu
bbb Downloaded：0: AVS motion compensation circuit of VLSI Design and Implementation of a standard based on the AVS motion compensation circuit efficient hardware structure, the design used 8 X 8 block-level pipelining, the normalized moti
Date : 2025-05-20 Size : 211kb User : sss

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