VHDL-FPGA-Verilog List Page 4104

VHDL-FPGA-Verilog list

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pcm1804_i2s_data_adjust2 Downloaded：0: I2S for pcm1804 adjusted data, so that I2S audio synchronization and FIFO does not overflow. Can automatically determine the FIFO- the state, by adjusting the output from the FIFO in the number of data in order to make t
Date : 2025-05-22 Size : 2kb User : WQL
amba_verilog Downloaded：1: IC design, arm within the realization of the source AMBA bridge, verilog language,
Date : 2025-05-22 Size : 18kb User : 伊路发
viterbi Downloaded：0: Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Date : 2025-05-22 Size : 61kb User : yaoyongshi
CIC Downloaded：0: Introduced the integral comb filter (CIC) design, there are procedures for compressed packets flow chart, using verilogHDL prepared on the ModelSim simulation results can be achieved very good
Date : 2025-05-22 Size : 150kb User : yaoyongshi
CORDIC Downloaded：0: Introduced the CORDIC digital computer design, using the verilogHDL, can be achieved on the ModelSim simulation, compressed package that contains the work of CORDIC structure diagram, a more detailed
Date : 2025-05-22 Size : 138kb User : yaoyongshi
add Downloaded：0: Introduced carry_chain_adder, carry_skip_adder, ipple_carry_adder three commonly used adder, using verilogHDL language, the use of ModelSim simulation software, compressed packet contains flowchart
Date : 2025-05-22 Size : 364kb User : yaoyongshi
divider Downloaded：0: Introduced the divider design, using verilogHDL language, the use of ModelSim simulation, compressed package that contains a flow chart
Date : 2025-05-22 Size : 82kb User : yaoyongshi
multiple Downloaded：0: This paper introduces some commonly used multiplier design, carry_save_mult, ripple_carry_mult such as, compressed package that contains the structure of flow chart, using verilogHDL language, using ModelSim simulation
Date : 2025-05-22 Size : 260kb User : yaoyongshi
couuseware_Verilog_QingHuaUniversity Downloaded：0: Meeting papers were laid on Tsinghua University VerilogHDl language courseware, electronic hardware engage in professional development can refer to reference!
Date : 2025-05-22 Size : 111kb User : 秦惜惜
sdram_controller Downloaded：0: SDRAM controller, after timing simulation, the correct function
Date : 2025-05-22 Size : 31kb User : 雷峰成
source Downloaded：0: Verilog design examples, and Wang Jinming matching of Verilog can be used.
Date : 2025-05-22 Size : 38kb User : 君懿
add Downloaded：0: The realization of a simple adder 16 and the test procedure Verilog code
Date : 2025-05-22 Size : 3kb User : 舒畅

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