VHDL-FPGA-Verilog List Page 4055

VHDL-FPGA-Verilog list

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VHDL1 Downloaded：0: VHDL study, the Taiwanese version of, well, learn quickly, ah ah
Date : 2025-05-24 Size : 546kb User :
jianpansaomiao__verilog Downloaded：0: Veriloghdl the preparation of a keyboard scanner
Date : 2025-05-24 Size : 717kb User : zhangzhenqi
ami_codes Downloaded：0: Coding ami, use hdl languages with documentation and test code
Date : 2025-05-24 Size : 449kb User : 聂样
all_digital_fm_receiver.tar Downloaded：0: All-digital FM receivers, including, test code, documentation, and source code
Date : 2025-05-24 Size : 654kb User : 聂样
design Downloaded：0: Mandarin source set-top boxes, including all source code, as well as detailed documentation, rare practical engineering, is now streaming film production
Date : 2025-05-24 Size : 409kb User : 聂样
ldpc_decoder_802_3an Downloaded：0: 802.3an ldpc code encoding, decoding the design, use of language VERILOG hdl, including test code,
Date : 2025-05-24 Size : 770kb User : 聂样
8b_10b Downloaded：0: VHDL prepared, 8b-10b codec design Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encodin
Date : 2025-05-24 Size : 71kb User : 聂样
experiment2_dsp_software_design Downloaded：0: The purpose of this experiment will be practical exercises how to use DSP EVM have弦波. Enable students to gain a better understanding of TMS320C6701 EVM development system
Date : 2025-05-24 Size : 50kb User : 宋涛
three_division_VHDL_programe Downloaded：0: According to the above one-third the frequency of thinking of writing procedures, 1/3 and 50 duty cycle procedures.
Date : 2025-05-24 Size : 3kb User : 宋涛
digital_clock Downloaded：0: Written by veriolg digital clock experiments with fixed time, to determine leap year, date display, download platform spantan3s400. Have a detailed annotation. Suitable for learning Verilog
Date : 2025-05-24 Size : 1.13mb User : 屠宁杰
divider Downloaded：1: This code used to realize the base 2 SRT divider design, you can realize more than 400MHz unsigned 32-bit fixed-point divider number (divisor, dividend and the remainder by the 16-bit integer and 16 fractional compositio
Date : 2025-05-24 Size : 2kb User : 朱秋玲
VHDL Downloaded：0: VHDL design of the circuit to simplify the problem of word document
Date : 2025-05-24 Size : 7kb User : 王分

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