VHDL-FPGA-Verilog List Page 4052

VHDL-FPGA-Verilog list

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usb_funct.tar Downloaded：0: Verilog language description of the USB 2.0 interface and new features in firmware.
Date : 2025-05-24 Size : 194kb User : 陈楚龙
16latch Downloaded：0: Latch 16, the procedure adopted quartusII software debugging
Date : 2025-05-24 Size : 1kb User : lvliangfei
FPGA Downloaded：0: FPGA adventure in the phenomenon, reducing the stability and power FPGA
Date : 2025-05-24 Size : 52kb User : zhangge
newsdram Downloaded：0: 8 Reading SDRAM verilog to write 8 procedures
Date : 2025-05-24 Size : 1.99mb User :
PALIC_8255 Downloaded：0: 8255 parallel interface chip a VHDL description can be integrated
Date : 2025-05-24 Size : 413kb User : luyingc
Pall_FIR Downloaded：0: FIR low-pass filter was designed in parallel algorithm design
Date : 2025-05-24 Size : 1.91mb User : luyingc
vhdl Downloaded：0: Pseudo-random sequence generator algorithm VHDL design of a pseudo-random sequence generator, using the generation polynomial for the 1+ X ^ 3+ X ^ 7. RESET has a client request and the two control registers client to ad
Date : 2025-05-24 Size : 1kb User : 文成
ise_book Downloaded：0: xilinx ISE code examples. ISE can be used directly to open
Date : 2025-05-24 Size : 7.89mb User : 罗
verilogvideocollection Downloaded：0: Verilog video collection procedures, verilog video collection procedures
Date : 2025-05-24 Size : 8kb User : 3060421006
frequency-phase_test_vhdl Downloaded：0: Phase tests, the frequency of testing, frequency counters, gate controller, showing decoding control VHDL procedures
Date : 2025-05-24 Size : 5kb User : 王充
LCDTest Downloaded：0: LCD1602 use VHDL to control the source, in the actual circuit in the test.
Date : 2025-05-24 Size : 2kb User : 尹邦坤
phone_count Downloaded：0: Telephone Billing
Date : 2025-05-24 Size : 4kb User : 张纪强

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