VHDL-FPGA-Verilog List Page 3974

VHDL-FPGA-Verilog list

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OFDMcode Downloaded：0: OFDM block of VHDL realize realize. Powerful
Date : 2025-06-02 Size : 38kb User : 付文强
dds Downloaded：0: CYCLONE II based on the procedure, DDS Function Generator principle. Realize the use of look-up table method. Members may refer to.
Date : 2025-06-02 Size : 226kb User : Yin
watch Downloaded：0: Based on CYCLONG II
Date : 2025-06-02 Size : 253kb User : Yin
Modelsim Downloaded：0: The good Quartus II and modelsim combine the simulation notes, which are more suitable for beginners and hope to help everyone!
Date : 2025-06-02 Size : 1.29mb User : 刘英
e001_vhdlsample Downloaded：0: VHDL learning of good example, beginners can be a serious study to deepen understanding. I learned, I feel very good.
Date : 2025-06-02 Size : 165kb User : chengpan
PLDszzds Downloaded：0: VHDL Test Guide can be used to make the pilot. Write very well, if you want to write something, you can reference.
Date : 2025-06-02 Size : 467kb User : chengpan
detect Downloaded：0: A sequence detector design. Procedure is not a problem, the key is to understand the thinking of state machine programming.
Date : 2025-06-02 Size : 1kb User : chengpan
SDR_SDRAM_controler_verilog Downloaded：0: Can use the generic SDRAM controller can be used in the FPGA, the SDR is the type of
Date : 2025-06-02 Size : 9kb User : 郑宏超
yw Downloaded：0: Own procedures for the lantern will know very well spent to make a really
Date : 2025-06-02 Size : 254kb User : 付长洲
chuan_to_bing Downloaded：0: 16 bit A/D conversion program, using MAX+PLUS2 to do the state machine, but not perfect, I hope you understand
Date : 2025-06-02 Size : 1kb User : 邓孟楠
can_IPCORE Downloaded：0: CAN bus IPCORE, using Verilog HDL language.
Date : 2025-06-02 Size : 60kb User : feifei
sin Downloaded：0: Sinusoidal signal generator procedures, used to write Verilog.
Date : 2025-06-02 Size : 2.41mb User : 112254

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