VHDL-FPGA-Verilog List Page 3969

VHDL-FPGA-Verilog list

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tushuguan Downloaded：0: - Functional Description- 1 credit card and identity generated only the corresponding element of the serial binary code sequence, as a simulation system of the input signal (in this case may be set to No. 8 students).- 2
Date : 2025-06-03 Size : 1kb User : leizi
61EDA_B307 Downloaded：0: Stepper Motor/DC Motor Controller Stepper Motor breakdown of rotation, with or without a breakdown rotation DC motor control
Date : 2025-06-03 Size : 114kb User : 李宁
VerilogHDLSource Downloaded：0: Verilog HDL Design Tutorial matching source
Date : 2025-06-03 Size : 166kb User : tmjdone
stepper_motor_control_design_example Downloaded：0: VHDL stepper motor control, whole-step half-step breakdown of the use of actel FPGA
Date : 2025-06-03 Size : 1.29mb User : 李宁
FT245BM Downloaded：0: This is a MAX II CPLD module using USB transmit FT245BM reading and writing process, using Verilog HDL language
Date : 2025-06-03 Size : 953kb User : 杨林成
sy Downloaded：0: Seven-Segment display decoder (functions: binary number will be thinking to seventh output signal, drive the digital display)
Date : 2025-06-03 Size : 4kb User : snow
crc16_ccitt Downloaded：0: crc_table.c is for reset seed (0000) crc_table_1.c is for reset seed (ffff) CRC16_D8_m.v is a verilog module of byte paralle crc.CRC16_D8_m_tb.v is the testbench file of above module.
Date : 2025-06-03 Size : 3kb User : 樊文杰
VERILOG_DEGISN_XYW Downloaded：0: From algorithm design to the realization of hardware logic (Xia Wen vreloge) Comparison of a classic book.
Date : 2025-06-03 Size : 2.26mb User : 刘浩
manchester_verilog Downloaded：0: Manchester codec Verilog code very good speed, but also occupy less resources.
Date : 2025-06-03 Size : 10kb User : 王鹏
hssdrc.tar Downloaded：0: High-speed SDRAM controller, and provide simulation testing procedures and more detailed documents.
Date : 2025-06-03 Size : 415kb User : yuhl
EDA_17392 Downloaded：0: A source EDA procedures, absolute certification. EDA suitable experimental boxes, and so on the basis of simulation experiment
Date : 2025-06-03 Size : 1.7mb User : 杨之皓
chap8 Downloaded：0: Commonly used classical typical circuit, such as the full adder, multiplier, how to reduce the resources
Date : 2025-06-03 Size : 4kb User : 王鹏

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