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VHDL-FPGA-Verilog list
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VHDL language written in the realization of digital down conversion, the whole project file, xlinx ise used
Date : 2025-06-16 Size : 1.78mb User : 杨斌

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Based on Multi-clock processing, the cross-clock domain processing advantages
Date : 2025-06-16 Size : 1kb User : xianren

Verilog HDL Digital Control System Design - Xian Jin- source code
Date : 2025-06-16 Size : 10.85mb User : 王洪亮

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CPLD_FPGA design and application, with examples of courseware
Date : 2025-06-16 Size : 20.74mb User : 王洪亮

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Easy-to-use UART communication module, and the preparation of the adoption of Verilog simulation, directly available
Date : 2025-06-16 Size : 711kb User : 李伟

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FPGA through the use of BT_656 interface 4-way video stream transmission method
Date : 2025-06-16 Size : 169kb User : Jimmysun

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Use VHDL to achieve four multiplier, not the realization of the direct use of multiplication, one to save resources, and secondly to improve the speed!
Date : 2025-06-16 Size : 1kb User :

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The realization of an adder design, the assumption that the input parameters for the A, B, the output of A, B and
Date : 2025-06-16 Size : 39kb User :

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To achieve 8-bit data input detection function, such as with the pre-enter the same number as output A, or output B
Date : 2025-06-16 Size : 45kb User :

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xilinx fpga do VGA driver signals Verilog source code, ise version 9.2,
Date : 2025-06-16 Size : 326kb User : bluefeifei

Verilog of 135 examples of classic design. Contains the source and description
Date : 2025-06-16 Size : 111kb User : 李林

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nc verilog instructions and examples for the utility to carry out simulation nc described in detail.
Date : 2025-06-16 Size : 578kb User : 李林
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