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VHDL-FPGA-Verilog list
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Embedded_risc
Downloaded:0
Embedded_risc IP CORE. VERY GOOD AS A STUDY FILE
Date
: 2025-06-18
Size
: 124kb
User
:
lijun
Keyboardcontroller
Downloaded:0
keyboardcontroller IP CORE. VERY GOOD AS A STUDY FILE
Date
: 2025-06-18
Size
: 7kb
User
:
lijun
FFTProcessor
Downloaded:0
IP CORE. VERY GOOD AS A STUDY FILE
Date
: 2025-06-18
Size
: 1.01mb
User
:
lijun
firewire
Downloaded:0
IP CORE. VERY GOOD AS A STUDY FILE
Date
: 2025-06-18
Size
: 103kb
User
:
lijun
VHDLtlight
Downloaded:0
Intelligent control of traffic lights. At the main road and side roads, as roads without the green light when the main road to maintain, when the roads when the roads a car through a green light, and in the shortest poss
Date
: 2025-06-18
Size
: 2kb
User
:
小白
ask
Downloaded:0
To provide a communication ASK modulation achieved using VHDL example, enclosing a corresponding VHDL source code.
Date
: 2025-06-18
Size
: 65kb
User
:
靳朝
run_watch
Downloaded:0
To provide a digital stopwatch the EDA design example, it is within the VHDL source code, and run the simulation of Fig.
Date
: 2025-06-18
Size
: 60kb
User
:
靳朝
DCT2IDCT2
Downloaded:0
CT2 IDCT2 transform C code. After successful testing for altera, bear fruit.
Date
: 2025-06-18
Size
: 1.12mb
User
:
金夕
cordiccos
Downloaded:0
Improved Iterative CORDIC algorithm cos structure, applicable to altera.
Date
: 2025-06-18
Size
: 8kb
User
:
金夕
multiply
Downloaded:0
Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.
Date
: 2025-06-18
Size
: 3kb
User
:
金夕
fir_parall
Downloaded:0
Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), through the verification.
Date
: 2025-06-18
Size
: 3kb
User
:
张堃
cpu
Downloaded:0
cpu VHDL Design and Implementation of multiplication addition subtraction
Date
: 2025-06-18
Size
: 1.92mb
User
:
郭红
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4310
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