VHDL-FPGA-Verilog List Page 3806

VHDL-FPGA-Verilog list

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poc1 Downloaded：0: poc of VHDL handshake signal to achieve the detailed design of interactive
Date : 2025-08-29 Size : 114kb User : 郭红
polar2rect_VHDL Downloaded：0: Atan is the codic algorithm virilog procedures, module is structured as follows: Core Structure: sc_corproc.vhd-> p2r_cordic.vhd-> p2r_cordicpipe.vhd
Date : 2025-08-29 Size : 3kb User : 张堃
vhdl Downloaded：0: VHDL-based preparation and implementation of the POC to achieve three-way handshake
Date : 2025-08-29 Size : 293kb User : 郭红
tAtan2Cordic Downloaded：0: Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.
Date : 2025-08-29 Size : 3kb User : 张堃
tSinCordic Downloaded：0: Sin is codic floating-point algorithm C procedures, including fixed-point and floating-point procedures, has been validated.
Date : 2025-08-29 Size : 5kb User : 张堃
butterworth_iir_verilog Downloaded：1: err
Date : 2025-08-29 Size : 10kb User : 张堃
xapp336_8b10b Downloaded：0: 8b10b reference design
Date : 2025-08-29 Size : 74kb User : 凌峰
xapp391_8b10b Downloaded：0: 8b10b design reference
Date : 2025-08-29 Size : 74kb User : 凌峰
vhdl4 Downloaded：0: The number of locks: 1. System has preset the initial password 00000001. 2. Enter the password with the stored password is the same, unlock success, showing a green light, or else unlock the failure to show a red light.
Date : 2025-08-29 Size : 246kb User : 宫逢源
newDPLLdesign Downloaded：0: The use of VHDL language design of digital phase-locked loop, pdf format, you can open
Date : 2025-08-29 Size : 544kb User : 国家
NewWayOfDPLLdesign Downloaded：0: The use of VHDL language design DPLL (digital phase-locked loop) of the relevant documents
Date : 2025-08-29 Size : 218kb User : 国家
DPLL2 Downloaded：0: All-digital phase-locked loop circuit development, using the VHDL language
Date : 2025-08-29 Size : 211kb User : 国家

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