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VHDL-FPGA-Verilog list
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NIOS_II_FLASH
Downloaded:0
NIOS_II in the use of FLASH, in SOPC design useful Oh
Date
: 2025-06-18
Size
: 595kb
User
:
renaifeng
SignalTapII_
Downloaded:0
SignalTapII use, in the FPGA design in a very good debugging tools
Date
: 2025-06-18
Size
: 660kb
User
:
renaifeng
sing
Downloaded:0
VHDL functionality to achieve a good singer, very good on the ~
Date
: 2025-06-18
Size
: 9kb
User
:
zhangyi
a1
Downloaded:0
FPGA-based B-data collection capabilities, according to the input image beam synchronization and frame synchronization signal used to control access to FIFO interrupt the operation of image data read and write!
Date
: 2025-06-18
Size
: 3kb
User
:
齐磊
ram
Downloaded:0
Memory modules generated, using 16-bit data bus, 5 to read and write address bus, asynchronous Clear!
Date
: 2025-06-18
Size
: 2kb
User
:
齐磊
nios_II_lab
Downloaded:0
The use of embedded digital clock nios2 the design and realization of the first to use quartus2 in sopc builder design CPU core, and then nios2 Zhongyong C language to realize the function of digital clock
Date
: 2025-06-18
Size
: 65kb
User
:
齐磊
AltrFir32
Downloaded:0
Altera With the company
Date
: 2025-06-18
Size
: 9kb
User
:
齐磊
MxIterative
Downloaded:0
The problem is that the linear shift register integrated question, given a N-long binary sequences, how to derive the sequence of series have the smallest linear shift register, that is the shortest linear shift register
Date
: 2025-06-18
Size
: 1kb
User
:
倪晨
VHDL
Downloaded:0
All kinds of finite state machine design. VHDL source code.
Date
: 2025-06-18
Size
: 12.6mb
User
:
邢开开
key_matrix44
Downloaded:0
FPGA EP1C6Q240C8 4* 4 keyboard module 4* 4 matrix keyboard, using scanning detection button
Date
: 2025-06-18
Size
: 272kb
User
:
lan
test_cnt
Downloaded:0
VHDL language is only testing procedures, the beginners to use than a simple call.
Date
: 2025-06-18
Size
: 3kb
User
:
韩风
DDR_SDRAM
Downloaded:0
Ddr use FPGA to read and write the source code can use the measured
Date
: 2025-06-18
Size
: 463kb
User
:
朱宝军
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