VHDL-FPGA-Verilog List Page 376

VHDL-FPGA-Verilog list

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code Downloaded：0: Realized the smart car is the walking function, able to walk a square stop
Date : 2025-06-10 Size : 5.98mb User : 周伟明
Gameone Downloaded：0: This stopwatch has two buttons (reset, start) press the reset button after the stopwatch is cleared, press the start button to start the timer, press the start button again to stop the clock, seven with two FPGA developm
Date : 2025-06-10 Size : 2.66mb User : XiaoLiuMang
Multiplier Downloaded：0: this a 8-bit Multiplier using 3 stages. after reset the 8 bit operands are loaded and the serial-parallel multiplication takes place.
Date : 2025-06-10 Size : 189kb User : hooman hematkhah
IDCT Downloaded：0: High Efficiency Video Coding(HEVC) is the currently developing video standard. In this article, a novel pipelined 2-D IDCT architecture based on HEVC is presented. By the analysis of the architecture design and adopting
Date : 2025-06-10 Size : 5kb User : 毕翔宇
my_counter Downloaded：0: this files are vhdl code
Date : 2025-06-10 Size : 2kb User : nasser
mips Downloaded：0: Based on the five-stage pipeline hardware architecture mips
Date : 2025-06-10 Size : 4kb User : 毕翔宇
alu Downloaded：0: this file is vhdl code of alu
Date : 2025-06-10 Size : 3kb User : nasser
FIR Downloaded：0: this file is vhdl code of fir filter
Date : 2025-06-10 Size : 40kb User : nasser
log4 Downloaded：0: this file is vhdl code of log4
Date : 2025-06-10 Size : 2kb User : nasser
motor Downloaded：0: this file is vhdl code of motor
Date : 2025-06-10 Size : 2kb User : nasser
calculator Downloaded：0: simple VHDL calculator
Date : 2025-06-10 Size : 1kb User : HB
divider Downloaded：0: FPGA Loop stitching Division
Date : 2025-06-10 Size : 1kb User : 段于

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