VHDL-FPGA-Verilog List Page 375

VHDL-FPGA-Verilog list

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2016 Downloaded：0: VHDL some projects can be used as a reference, water lights, serial port FIR, keypad, digital control and so on
Date : 2025-12-29 Size : 5.75mb User : 张任
new_project Downloaded：0: This design is a vending machine control system design based on FPGA. The design uses FPGA as a master, vending machine control system design. Analog vending machine cargo information storage, selection and purchase of g
Date : 2025-12-29 Size : 3.88mb User : 张任
usart_txd_mk3 Downloaded：0: Using Verilog write serial transmission program, we hope to be of some use
Date : 2025-12-29 Size : 3.06mb User : 缪家骏
Vending-Machine-using-Moore Downloaded：0: Vending Machine simulation using Moore sequence
Date : 2025-12-29 Size : 45kb User : Japerski
Mealy Downloaded：0: Example of Mealy sequence in VHDL
Date : 2025-12-29 Size : 37kb User : Japerski
Basic_Examples Downloaded：0: Basic syntax and codes used in VHDL
Date : 2025-12-29 Size : 1kb User : Japerski
cy4ex14 Downloaded：0: verilog fpga
Date : 2025-12-29 Size : 4.8mb User : 姜晓明
VHDL-Design-of-31-bit-Pipelined-Adder Downloaded：0: The design runs at 316.46 MHz and uses 125 LEs.
Date : 2025-12-29 Size : 215kb User : hooman hematkhah
8-bit-Multiplier Downloaded：0: Multiplication is performed in three stages. After reset, the 8-bit operands are “loaded” and the product register is set to zero. In the second stage, s1, the actual serial-parallel multiplication takes place. In the th
Date : 2025-12-29 Size : 189kb User : hooman hematkhah
I2C Downloaded：0: Can fully realize the I2C, a detailed code notes, very easy to understand.
Date : 2025-12-29 Size : 6.86mb User : glywhh
8-bit-Restoring-Divider Downloaded：0: Division is performed in four stages. After reset, the 8-bit numerator is “loaded” in the remainder register, the 6-bit denominator is loaded and aligned (by 2N− 1 for a N bit numerator), and the quotient register i
Date : 2025-12-29 Size : 224kb User : hooman hematkhah
Anderson--Algorithm Downloaded：0: We assume that denominator and numerator are normalized as, for instance, typical for floating-point mantissa values, to the interval 1 ≤ N, D < 2. This normalization step may require essential addition resources (leadin
Date : 2025-12-29 Size : 194kb User : hooman hematkhah

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