VHDL-FPGA-Verilog List Page 3689

VHDL-FPGA-Verilog list

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DE2_TV Downloaded：0: based DE2 development board ,it is vhdl resourse code
Date : 2025-06-22 Size : 137kb User : zhaoqian
cpld Downloaded：0: ATEREAL EPM1270T144C5N CPLD-based pressure sensor data acquisition source Quartus II development software
Date : 2025-06-22 Size : 301kb User : 胡兵
myclock Downloaded：0: VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to tim
Date : 2025-06-22 Size : 374kb User : 旭东
division Downloaded：0: The design of non - integer frequency divider is completed by dividing frequency ratio cross - frequency and accumulator frequency division. - Points were staggered method and frequency than the frequency accumulator law
Date : 2025-06-22 Size : 28kb User : 旭东
cpu Downloaded：0: VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the final design of the micro-operation microinstruction to ve
Date : 2025-06-22 Size : 1.21mb User : Rachel
DW8051_verilog Downloaded：0: DW8051 microcontroller design, HDL design, detailed design of the HDL
Date : 2025-06-22 Size : 133kb User : liaobin
RTC_Test_Top Downloaded：0: With Actel' s Fusion Series FPGA development of experimental procedures RTC
Date : 2025-06-22 Size : 1kb User : 毕京鹏
hdl Downloaded：0: Fusion with Actel s FPGA development series LCD Experimental procedures
Date : 2025-06-22 Size : 3kb User : 毕京鹏
video_control_procedure Downloaded：0: Using VHDL video control procedures (the achievement of the image acquisition and compression)
Date : 2025-06-22 Size : 412kb User : huangya
Video_Compression_IPCore.RAR Downloaded：0: Video Compression IPCore
Date : 2025-06-22 Size : 158kb User : huangya
CC2500programmingusingAlteraFPGA Downloaded：0: This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.
Date : 2025-06-22 Size : 7kb User : Mahadevan
4 Downloaded：0: Verilog write 8-bit CLA
Date : 2025-06-22 Size : 1kb User : 孔祥

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