VHDL-FPGA-Verilog List Page 3681

VHDL-FPGA-Verilog list

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crc16 Downloaded：0: crc16 module for SDIO DAT line calculation
Date : 2025-06-23 Size : 1kb User : kantengri
ncr Downloaded：0: module to wait 2 clocks for SD card
Date : 2025-06-23 Size : 1kb User : kantengri
wait_data Downloaded：0: module to wait data on DAT line SDIO mode
Date : 2025-06-23 Size : 1kb User : kantengri
send_cmd Downloaded：0: SD card SDIO module send command and read response
Date : 2025-06-23 Size : 1kb User : kantengri
FiltroDSP Downloaded：0: This sources implement a 8-bit FIR Filter with selectable coefficent rom.
Date : 2025-06-23 Size : 1.51mb User : Jose
MultiplicadorSHIF Downloaded：0: This code creates a 8 bit full multiplier.
Date : 2025-06-23 Size : 1.34mb User : Jose
dds Downloaded：0: The use of EDA hardware description language to achieve the DDS functions, using VC++6.0 to achieve sinx, cosx data collection, software used as the carrier to achieve quart2
Date : 2025-06-23 Size : 727kb User : 游智超
uart_regs Downloaded：0: Altera IP uart_regs core
Date : 2025-06-23 Size : 919kb User : 寻宝人
Project Downloaded：0: RAM，DualPortRAM
Date : 2025-06-23 Size : 135kb User : 寻宝人
Project Downloaded：0: 8B10B codeer
Date : 2025-06-23 Size : 157kb User : 寻宝人
source Downloaded：0: modelsim simulation
Date : 2025-06-23 Size : 333kb User : 寻宝人
FHT_example Downloaded：0: Altera FPGACPLD FHT_example design
Date : 2025-06-23 Size : 224kb User : 寻宝人

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