VHDL-FPGA-Verilog List Page 360

VHDL-FPGA-Verilog list

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write Downloaded：0: Use golang generate a coe file to initialize rom. Wherein the randomly generated value as the initial value 1
Date : 2025-06-09 Size : 1kb User :
source Downloaded：0: FPGA serial, verilog HDL serial transceiver procedures
Date : 2025-06-09 Size : 2kb User : zkybs
shuzipaobiao_all Downloaded：1: VErilog source, digital stopwatch digital display, control buttons
Date : 2025-06-09 Size : 843kb User : June
yiweijicunqi Downloaded：0: Shift register schematic design, based quartusII software.
Date : 2025-06-09 Size : 270kb User : June
DE2-115_labs_verilog Downloaded：0: PDF format Verilog, DE2-115 plate course
Date : 2025-06-09 Size : 1.33mb User : June
DE2-115_labs_vhdl Downloaded：0: , Lab-exercise of PDF course DE2-115 board
Date : 2025-06-09 Size : 1.47mb User : June
DE2_115_pin_assignments Downloaded：0: de2-115 configuration pins, quartusII settings
Date : 2025-06-09 Size : 5kb User : June
GTX4 Downloaded：1: Fiber optic transmitter receiver module, verilog written primarily for transmitting and receiving the optical fiber, wavelength 1310nm
Date : 2025-06-09 Size : 5.24mb User : 维斯摩尔
liushuideng Downloaded：0: Water lights, control direction, the system clock frequency, odd even flashing
Date : 2025-06-09 Size : 2kb User : 陈宇璐
pinlvji-design-VHDL Downloaded：0: The use of Altera EP2C35 series FPGA chip using the SOPC-NIOSII-EP2C35 board design and simulation of a digital frequency meter, for 1Hz ~ 250KHz pulse frequency measurement using such as precision measurement that the e
Date : 2025-06-09 Size : 1.3mb User : 淡然
breath_led Downloaded：0: verilog breath led sourece code
Date : 2025-06-09 Size : 358kb User : YesterDAY
buzzer_sos Downloaded：0: buzzer code verilog
Date : 2025-06-09 Size : 349kb User : YesterDAY

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